From 05b1b7787b7d59607d8ccdfd8ff2fb1f349cb89b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 6 Apr 2020 13:11:50 +0200 Subject: [PATCH] interconnect/csr, wishbone: use reset_less on datapath signals. --- litex/soc/interconnect/csr_bus.py | 7 +++++-- litex/soc/interconnect/wishbone.py | 16 ++++++++++------ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index c3f3bde79..2e804c8df 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -39,6 +39,9 @@ class Interface(Record): Record.__init__(self, set_layout_parameters(_layout, data_width = data_width, address_width = address_width)) + self.adr.reset_less = True + self.dat_w.reset_less = True + self.dat_r.reset_less = True @classmethod def like(self, other): @@ -120,7 +123,7 @@ class SRAM(Module): adr_shift = log2_int(bus.alignment//32) if word_bits: - word_index = Signal(word_bits) + word_index = Signal(word_bits, reset_less=True) word_expanded = Signal(csrw_per_memw*data_width) self.sync += word_index.eq(self.bus.adr[adr_shift:adr_shift+word_bits]) self.comb += [ @@ -132,7 +135,7 @@ class SRAM(Module): if not read_only: wregs = [] for i in range(csrw_per_memw-1): - wreg = Signal(data_width) + wreg = Signal(data_width, reset_less=True) self.sync += If(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == i), wreg.eq(self.bus.dat_w)) wregs.append(wreg) memword_chunks = [self.bus.dat_w] + list(reversed(wregs)) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 128496e28..7c82d066f 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -38,9 +38,13 @@ class Interface(Record): self.data_width = data_width self.adr_width = adr_width Record.__init__(self, set_layout_parameters(_layout, - adr_width=adr_width, - data_width=data_width, - sel_width=data_width//8)) + adr_width = adr_width, + data_width = data_width, + sel_width = data_width//8)) + self.adr.reset_less = True + self.dat_w.reset_less = True + self.dat_r.reset_less = True + self.sel.reset_less = True @staticmethod def like(other): @@ -311,7 +315,7 @@ class DownConverter(Module): self.comb += Case(counter, cases) - cached_data = Signal(dw_from) + cached_data = Signal(dw_from, reset_less=True) self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r)) self.sync += \ If(read & counter_ce, @@ -553,7 +557,7 @@ class Cache(Module): if adr_offset is None: adr_offset_r = None else: - adr_offset_r = Signal(offsetbits) + adr_offset_r = Signal(offsetbits, reset_less=True) self.sync += adr_offset_r.eq(adr_offset) self.comb += [ @@ -707,7 +711,7 @@ class SRAM(Module): # generate ack self.sync += [ self.bus.ack.eq(0), - If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1)) + If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1)) ]