From 05bc2885e98cdf9103a5c93736f054d2a334b938 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:49:39 +0200 Subject: [PATCH] Call finalize() after CRG creation --- mibuild/altera_quartus.py | 1 - mibuild/generic_platform.py | 2 ++ mibuild/xilinx_ise.py | 1 - 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index dbb336a75..4fc785509 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -74,7 +74,6 @@ quartus_sta {build_name}.qpf class AlteraQuartusPlatform(GenericPlatform): def build(self, fragment, build_dir="build", build_name="top", quartus_path="/opt/Altera", run=True): - self.finalize(fragment) tools.mkdir_noerror(build_dir) os.chdir(build_dir) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 2feb70e4d..86c12651e 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -209,6 +209,8 @@ class GenericPlatform: frag = fragment + crg.get_fragment() else: frag = fragment + # finalize + self.finalize(fragment) # generate Verilog src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, create_clock_domains=False, **kwargs) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 2ff3abec3..69306f5ae 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -151,7 +151,6 @@ class XilinxISEPlatform(GenericPlatform): def build(self, fragment, build_dir="build", build_name="top", ise_path="/opt/Xilinx", source=True, run=True): - self.finalize(fragment) tools.mkdir_noerror(build_dir) os.chdir(build_dir)