diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index b73cffbb9..adb6f07cb 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -55,6 +55,7 @@ GCC_FLAGS = { # BlackParrotRV64 ---------------------------------------------------------------------------------- class BlackParrotRV64(CPU): + family = "riscv" name = "blackparrot" human_name = "BlackParrotRV64[imafd]" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/cv32e40p/core.py b/litex/soc/cores/cpu/cv32e40p/core.py index 0c16bb310..6bf6ce157 100644 --- a/litex/soc/cores/cpu/cv32e40p/core.py +++ b/litex/soc/cores/cpu/cv32e40p/core.py @@ -355,6 +355,7 @@ class DebugModule(Module): # CV32E40P ----------------------------------------------------------------------------------------- class CV32E40P(CPU): + family = "riscv" name = "cv32e40p" human_name = "CV32E40P" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/femtorv/core.py b/litex/soc/cores/cpu/femtorv/core.py index 82a7d7026..34dd2b4a2 100644 --- a/litex/soc/cores/cpu/femtorv/core.py +++ b/litex/soc/cores/cpu/femtorv/core.py @@ -18,6 +18,7 @@ CPU_VARIANTS = ["standard"] # FemtoRV ------------------------------------------------------------------------------------------ class FemtoRV(CPU): + family = "riscv" name = "femtorv" human_name = "FemtoRV" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index 796740c46..f4ee87d82 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -98,6 +98,7 @@ class OBI2Wishbone(Module): # Ibex --------------------------------------------------------------------------------------------- class Ibex(CPU): + family = "riscv" name = "ibex" human_name = "Ibex" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index f7ac550b0..bf26e433c 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -23,6 +23,7 @@ CPU_VARIANTS = ["minimal", "lite", "standard"] # LM32 --------------------------------------------------------------------------------------------- class LM32(CPU): + family = "lm32" name = "lm32" human_name = "LM32" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 4dde10a78..8f2e5375c 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -25,6 +25,7 @@ CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq" # Microwatt ---------------------------------------------------------------------------------------- class Microwatt(CPU): + family = "powerpc" name = "microwatt" human_name = "Microwatt" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 54edd9373..dfe9ce75e 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -21,6 +21,7 @@ CPU_VARIANTS = ["standard"] # Minerva ------------------------------------------------------------------------------------------ class Minerva(CPU): + family = "riscv" name = "minerva" human_name = "Minerva" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index e945be05d..67e993856 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -22,6 +22,7 @@ CPU_VARIANTS = ["standard", "standard+fpu", "linux", "linux+fpu", "linux+smp", " # Mor1kx ------------------------------------------------------------------------------------------- class MOR1KX(CPU): + family = "or1k" name = "mor1kx" human_name = "MOR1KX" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index c62c20c30..3706697db 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -37,6 +37,7 @@ GCC_FLAGS = { # PicoRV32 ----------------------------------------------------------------------------------------- class PicoRV32(CPU): + family = "riscv" name = "picorv32" human_name = "PicoRV32" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 308eeb845..fca3b7388 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -83,6 +83,7 @@ CPU_SIZE_PARAMS = { # Rocket RV64 -------------------------------------------------------------------------------------- class RocketRV64(CPU): + family = "riscv" name = "rocket" human_name = "RocketRV64[imac]" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index 4c6c0792a..01f3a42f1 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -20,6 +20,7 @@ CPU_VARIANTS = ["standard"] # SERV --------------------------------------------------------------------------------------------- class SERV(CPU): + family = "riscv" name = "serv" human_name = "SERV" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index c3d433951..ab6404a11 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -93,6 +93,7 @@ class VexRiscvTimer(Module, AutoCSR): # VexRiscv ----------------------------------------------------------------------------------------- class VexRiscv(CPU, AutoCSR): + family = "riscv" name = "vexriscv" human_name = "VexRiscv" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 44deb4ee4..22ecfab97 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -30,6 +30,7 @@ CPU_VARIANTS = { # VexRiscv SMP ------------------------------------------------------------------------------------- class VexRiscvSMP(CPU): + family = "riscv" name = "vexriscv" human_name = "VexRiscv SMP" variants = CPU_VARIANTS diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py index ef4239d59..28f743a23 100644 --- a/litex/soc/cores/cpu/zynq7000/core.py +++ b/litex/soc/cores/cpu/zynq7000/core.py @@ -19,6 +19,7 @@ from litex.soc.cores.cpu import CPU class Zynq7000(CPU): variants = ["standard"] + family = "arm" name = "zynq7000" human_name = "Zynq7000" data_width = 32 diff --git a/litex/soc/integration/export.py b/litex/soc/integration/export.py index f74fe57d4..c01ac191e 100644 --- a/litex/soc/integration/export.py +++ b/litex/soc/integration/export.py @@ -92,6 +92,7 @@ def get_cpu_mak(cpu, compile_software): return [ ("TRIPLE", select_triple(triple)), ("CPU", cpu.name), + ("CPUFAMILY", cpu.family), ("CPUFLAGS", flags), ("CPUENDIANNESS", cpu.endianness), ("CLANG", str(int(clang))), diff --git a/litex/soc/software/libc/Makefile b/litex/soc/software/libc/Makefile index 4a4fb999b..8329991b9 100644 --- a/litex/soc/software/libc/Makefile +++ b/litex/soc/software/libc/Makefile @@ -3,24 +3,10 @@ include $(SOC_DIRECTORY)/software/common.mak all: libc.a stdio.c.o missing.c.o -CPUFAMILY= - CFLAGS = $(COMMONFLAGS) -fexceptions -Wpragmas -# FIXME: Generate from Python. -ifneq ($(findstring $(CPU), serv femtorv picorv32 minerva vexriscv vexriscv_smp ibex cv32e40p rocket blackparrot),) - CPUFAMILY = riscv -else ifeq ($(CPU), lm32) - CPUFAMILY = lm32 -else ifeq ($(CPU), mor1kx) - CPUFAMILY = or1k -else ifeq ($(CPU), microwatt) - CPUFAMILY = powerpc +ifeq ($(CPU), microwatt) CFLAGS += -DLONG_LONG_MIN=LLONG_MIN -DLONG_LONG_MAX=LLONG_MAX -DLONG_LONG_MIN=LLONG_MIN -DULONG_LONG_MAX=ULLONG_MAX -else ifeq ($(CPU), zynq7000) - CPUFAMILY = arm -else - $(error Unsupported CPU) endif define CROSSFILE