diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 12e2d0574..7c0529f0f 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -97,7 +97,7 @@ CPU_VARIANTS = {
     "linuxd" :    [],
     "linuxq" :    [],
 }
-CPU_VARIANTS_EXTENSIONS = ["debug", "no-dsp"]
+CPU_VARIANTS_EXTENSIONS = ["debug", "no-dsp", "ghdl"]
 
 class InvalidCPUVariantError(ValueError):
     def __init__(self, variant):
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 513ae7083..b0dee76dc 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -11,7 +11,7 @@ from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
 
-CPU_VARIANTS = ["standard"]
+CPU_VARIANTS = ["standard", "standard+ghdl"]
 
 
 class Microwatt(CPU):
@@ -94,7 +94,7 @@ class Microwatt(CPU):
         )
 
         # add vhdl sources
-        self.add_sources(platform)
+        self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
 
     def set_reset_address(self, reset_address):
         assert not hasattr(self, "reset_address")