From 0696b409aba8a44fadda3aff0a23fb6c74aeb694 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Jul 2020 18:37:23 +0200
Subject: [PATCH] CHANGES: update.

---
 CHANGES | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGES b/CHANGES
index ed4399a74..836fead16 100644
--- a/CHANGES
+++ b/CHANGES
@@ -27,6 +27,7 @@
 	- Revert to a single crt0 (avoid ctr/xip variants).
 	- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
 	- Add AXI-Lite bus standard support.
+	- Add VexRiscv SMP CPU support.
 
 	[> API changes/Deprecation
 	--------------------------