diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index ae5db539e..6df91378e 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -92,8 +92,8 @@ class BlackParrotRV64(CPU): self.cpu_params = dict( # Clk / Rst. - i_clk_i = ClockSignal(), - i_reset_i = ResetSignal() | self.reset, + i_clk_i = ClockSignal("sys"), + i_reset_i = ResetSignal("sys") | self.reset, # Wishbone (I/D). i_wbm_dat_i = idbus.dat_r, diff --git a/litex/soc/cores/cpu/cv32e40p/core.py b/litex/soc/cores/cpu/cv32e40p/core.py index eb24f97e2..0c16bb310 100644 --- a/litex/soc/cores/cpu/cv32e40p/core.py +++ b/litex/soc/cores/cpu/cv32e40p/core.py @@ -240,8 +240,8 @@ class TraceDebugger(Module): self.trace_params = dict( # Clk / Rst. - i_clk_i = ClockSignal(), - i_rst_ni = ~ResetSignal(), + i_clk_i = ClockSignal("sys"), + i_rst_ni = ~ResetSignal("sys"), i_test_mode_i = 0, # CPU Interface. @@ -309,8 +309,8 @@ class DebugModule(Module): self.dm_params = dict( # Clk / Rst. - i_clk = ClockSignal(), - i_rst_n = ~ResetSignal(), + i_clk = ClockSignal("sys"), + i_rst_n = ~ResetSignal("sys"), o_ndmreset = self.ndmreset, o_debug_req = self.debug_req, @@ -398,8 +398,8 @@ class CV32E40P(CPU): self.cpu_params = dict( # Clk / Rst. - i_clk_i = ClockSignal(), - i_rst_ni = ~ResetSignal(), + i_clk_i = ClockSignal("sys"), + i_rst_ni = ~ResetSignal("sys"), # Controls. i_clock_en_i = 1, diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index 7ed738e39..796740c46 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -143,8 +143,8 @@ class Ibex(CPU): i_hart_id_i = 0, # Clk/Rst. - i_clk_i = ClockSignal(), - i_rst_ni = ~ResetSignal(), + i_clk_i = ClockSignal("sys"), + i_rst_ni = ~ResetSignal("sys"), # Instruction bus. o_instr_req_o = ibus.req, diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 4d1fed0d4..4c3c20a31 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -78,8 +78,8 @@ class Microwatt(CPU): self.cpu_params = dict( # Clk / Rst. - i_clk = ClockSignal(), - i_rst = ResetSignal() | self.reset, + i_clk = ClockSignal("sys"), + i_rst = ResetSignal("sys") | self.reset, # IBus. i_wishbone_insn_dat_r = ibus.dat_r, @@ -235,8 +235,8 @@ class XICSSlave(Module, AutoCSR): self.icp_params = dict( # Clk / Rst. - i_clk = ClockSignal(), - i_rst = ResetSignal(), + i_clk = ClockSignal("sys"), + i_rst = ResetSignal("sys"), # Wishbone Bus. o_wishbone_dat_r = icp_bus.dat_r, @@ -257,8 +257,8 @@ class XICSSlave(Module, AutoCSR): self.ics_params = dict( # Clk / Rst. - i_clk = ClockSignal(), - i_rst = ResetSignal(), + i_clk = ClockSignal("sys"), + i_rst = ResetSignal("sys"), # Wishbone Bus. o_wishbone_dat_r = ics_bus.dat_r, diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 0a384736d..54edd9373 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -53,8 +53,8 @@ class Minerva(CPU): self.cpu_params = dict( # Clk / Rst. - i_clk = ClockSignal(), - i_rst = ResetSignal() | self.reset, + i_clk = ClockSignal("sys"), + i_rst = ResetSignal("sys") | self.reset, # IRQ. i_timer_interrupt = 0, diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 50c675840..e945be05d 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -154,8 +154,8 @@ class MOR1KX(CPU): **cpu_args, # Clk / Rst. - i_clk = ClockSignal(), - i_rst = ResetSignal() | self.reset, + i_clk = ClockSignal("sys"), + i_rst = ResetSignal("sys") | self.reset, # IRQ. i_irq_i=self.interrupt, diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 9ad28ef44..c62c20c30 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -123,8 +123,8 @@ class PicoRV32(CPU): self.cpu_params.update( # Clk / Rst. - i_clk = ClockSignal(), - i_resetn = ~(ResetSignal() | self.reset), + i_clk = ClockSignal("sys"), + i_resetn = ~(ResetSignal("sys") | self.reset), # Trap. o_trap = self.trap, diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 80ec86ef8..940414446 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -128,8 +128,8 @@ class RocketRV64(CPU): self.cpu_params = dict( # Clk / Rst. - i_clock = ClockSignal(), - i_reset = ResetSignal() | self.reset, + i_clock = ClockSignal("sys"), + i_reset = ResetSignal("sys") | self.reset, # Debug (ignored). i_resetctrl_hartIsInReset_0 = Open(), diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 45cd811e2..a3dc324cd 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -136,8 +136,8 @@ class VexRiscv(CPU, AutoCSR): # # # self.cpu_params = dict( - i_clk = ClockSignal(), - i_reset = ResetSignal() | self.reset, + i_clk = ClockSignal("sys"), + i_reset = ResetSignal("sys") | self.reset, i_externalInterruptArray = self.interrupt, i_timerInterrupt = 0, @@ -310,8 +310,8 @@ class VexRiscv(CPU, AutoCSR): i_rsp_ready = cfu_bus.rsp.ready, o_rsp_payload_response_ok = cfu_bus.rsp.payload.response_ok, o_rsp_payload_outputs_0 = cfu_bus.rsp.payload.outputs_0, - i_clk = ClockSignal(), - i_reset = ResetSignal(), + i_clk = ClockSignal("sys"), + i_reset = ResetSignal("sys"), ) self.platform.add_source(cfu_filename)