From 070c4cd3875491d43c4c0f6736140ac2177878ec Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 26 Nov 2024 17:40:03 +0100 Subject: [PATCH] cores/cpu/vexiiriscv: Add PMP support The RISC-V PMP feature can now be enabled via --vexii-args="--pmp-size=8" for instance. TOR support can be disabled via --pmp-tor-disable to save area / timings --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 5a97c4642..d3cbbe090 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -156,7 +156,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "ca10ab58", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "b4269ddc", args.update_repo) if not args.cpu_variant: args.cpu_variant = "standard"