From 0720ffb404ea09c2eab59103b44ecab5a71d9426 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 17 May 2024 10:00:24 +0200 Subject: [PATCH] Update vexii --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 83743b914..18ebd7f68 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -130,7 +130,7 @@ class VexiiRiscv(CPU): print(args) if args.update_repo != "no": - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "139a1bd6" if args.update_repo=="recommended" else None) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "8a239d10" if args.update_repo=="recommended" else None)