From 073641faa1942b41b0f143d3b164b95ef8214cda Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 4 Mar 2015 00:46:24 +0000 Subject: [PATCH] litesata: fix permissions and imports --- misoclib/mem/litesata/example_designs/build/.keep_me | 0 misoclib/mem/litesata/example_designs/make.py | 0 .../mem/litesata/example_designs/platforms/verilog_backend.py | 4 ++-- 3 files changed, 2 insertions(+), 2 deletions(-) create mode 100644 misoclib/mem/litesata/example_designs/build/.keep_me mode change 100644 => 100755 misoclib/mem/litesata/example_designs/make.py diff --git a/misoclib/mem/litesata/example_designs/build/.keep_me b/misoclib/mem/litesata/example_designs/build/.keep_me new file mode 100644 index 000000000..e69de29bb diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py old mode 100644 new mode 100755 diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py index f531c901d..7302a0eb2 100644 --- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py +++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py @@ -1,6 +1,6 @@ from mibuild.generic_platform import * -from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_vivado import XilinxVivadoPlatform +from mibuild.xilinx.common import CRG_DS +from mibuild.xilinx.vivado import XilinxVivadoPlatform _io = [ ("sys_clk", 0, Pins("X")),