diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
index dd9c986b7..d82f8af1c 100644
--- a/examples/corelogic_conv.py
+++ b/examples/corelogic_conv.py
@@ -1,8 +1,8 @@
 from migen.fhdl import verilog
 from migen.corelogic import divider
 
-d1 = divider.Inst(16)
-d2 = divider.Inst(16)
+d1 = divider.Divider(16)
+d2 = divider.Divider(16)
 frag = d1.get_fragment() + d2.get_fragment()
 o = verilog.convert(frag, {
 	d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index b1df3b724..041894b11 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -29,7 +29,7 @@ class Arbiter:
 	def __init__(self, masters, target):
 		self.masters = masters
 		self.target = target
-		self.rr = roundrobin.Inst(len(self.masters))
+		self.rr = roundrobin.RoundRobin(len(self.masters))
 
 	def get_fragment(self):
 		comb = []
diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
index 497cac682..a0cd56292 100644
--- a/migen/bus/wishbone2csr.py
+++ b/migen/bus/wishbone2csr.py
@@ -3,11 +3,11 @@ from migen.bus import csr
 from migen.fhdl.structure import *
 from migen.corelogic import timeline
 
-class Inst():
+class WB2CSR():
 	def __init__(self):
 		self.wishbone = wishbone.Slave("to_csr")
 		self.csr = csr.Master("from_wishbone")
-		self.timeline = timeline.Inst(self.wishbone.cyc_i & self.wishbone.stb_i,
+		self.timeline = timeline.Timeline(self.wishbone.cyc_i & self.wishbone.stb_i,
 			[(1, [self.csr.we_o.eq(self.wishbone.we_i)]),
 			(2, [self.wishbone.ack_o.eq(1)]),
 			(3, [self.wishbone.ack_o.eq(0)])])
diff --git a/migen/corelogic/divider.py b/migen/corelogic/divider.py
index fb2214754..50b4af18f 100644
--- a/migen/corelogic/divider.py
+++ b/migen/corelogic/divider.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class Divider:
 	def __init__(self, w):
 		self.w = w
 		
diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py
index af1e057dd..1f0e5527d 100644
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class RoundRobin:
 	def __init__(self, n):
 		self.n = n
 		self.bn = bits_for(self.n-1)
diff --git a/migen/corelogic/timeline.py b/migen/corelogic/timeline.py
index f47e188f5..0bbbdd1bf 100644
--- a/migen/corelogic/timeline.py
+++ b/migen/corelogic/timeline.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class Timeline:
 	def __init__(self, trigger, events):
 		self.trigger = trigger
 		self.events = events
diff --git a/migen/flow/ala.py b/migen/flow/ala.py
index 649c8cf65..e472f5445 100644
--- a/migen/flow/ala.py
+++ b/migen/flow/ala.py
@@ -60,7 +60,7 @@ class NE(_SimpleBinary):
 
 class DivMod(Actor):
 	def __init__(self, width):
-		self.div = divider.Inst(width)
+		self.div = divider.Divider(width)
 		Actor.__init__(self,
 			SchedulingModel(SchedulingModel.SEQUENTIAL, width),
 			("operands", Sink, [("dividend", self.div.dividend_i), ("divisor", self.div.divisor_i)]),