From 07bc589c414fb036ccdaee87b77aa4725123dfc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Mon, 20 Jul 2020 15:17:56 +0200 Subject: [PATCH] fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at: https://github.com/antmicro/litex-buildenv/commit/cc003bef3ac1407f9788ec8b7cc52d5981f8364a and litex bumped to 4a18b828bc81522a654f51a73f20faece4dc313c, with options: CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net The only difference in Verilog is that we avoid creating new Interface and doing `new_interface.connect(interface)`, so this shouldn't make any difference, but this somehow generates the error in Vivado (tested on v2018.3 and v2019.2). --- litex/soc/integration/soc.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 6e64e8493..e7d2886d1 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -282,12 +282,15 @@ class SoCBusHandler(Module): assert direction in ["m2s", "s2m"] if isinstance(interface, wishbone.Interface): - new_interface = wishbone.Interface(data_width=self.data_width) - if direction == "m2s": - converter = wishbone.Converter(master=interface, slave=new_interface) - if direction == "s2m": - converter = wishbone.Converter(master=new_interface, slave=interface) - self.submodules += converter + if interface.data_width != self.data_width: + new_interface = wishbone.Interface(data_width=self.data_width) + if direction == "m2s": + converter = wishbone.Converter(master=interface, slave=new_interface) + if direction == "s2m": + converter = wishbone.Converter(master=new_interface, slave=interface) + self.submodules += converter + else: + new_interface = interface elif isinstance(interface, axi.AXILiteInterface): # Data width conversion intermediate = axi.AXILiteInterface(data_width=self.data_width)