From 07c7f664cfb68e9392accfaf45c767e4fb718c13 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 18 Jan 2022 11:34:12 +0100 Subject: [PATCH] integration/soc/add_sdram: Set default l2_cache_reverse value to False. For correct operation of Framebuffer + CPU writes, l2_cache_reverse has to be set to False on targets. Set it to False by default in LiteX to avoid this. --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 9d3741b2c..b5034d0ff 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1262,7 +1262,7 @@ class LiteXSoC(SoC): def add_sdram(self, name, phy, module, origin=None, size=None, with_bist=False, with_soc_interconnect=True, l2_cache_size = 8192, l2_cache_min_data_width = 128, - l2_cache_reverse = True, + l2_cache_reverse = False, l2_cache_full_memory_we = True, **kwargs):