From 07cfda119daf5e302e36a7b68cd26e4c76e6ef37 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Fri, 5 Apr 2024 10:04:39 +1100 Subject: [PATCH] interconnect/wishbone: check err in simulation --- litex/soc/interconnect/wishbone.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 943263f93..4ef9e55ef 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -90,6 +90,8 @@ class Interface(Record): yield self.bte.eq(bte) yield self.we.eq(1) yield from self._do_transaction() + if (yield self.err): + raise ValueError("bus error") def read(self, adr, cti=None, bte=None): yield self.adr.eq(adr) @@ -99,6 +101,8 @@ class Interface(Record): if bte is not None: yield self.bte.eq(bte) yield from self._do_transaction() + if (yield self.err): + raise ValueError("bus error") return (yield self.dat_r) def get_ios(self, bus_name="wb"):