From 07e4c183cd0752df5bf98662c07394365eef4c81 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 12 Sep 2018 06:02:23 +0200 Subject: [PATCH] cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) --- .../soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v | 4 ++-- litex/soc/integration/cpu_interface.py | 5 +---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v b/litex/soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v index 83d9d97f4..b9620d6c9 100644 --- a/litex/soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v +++ b/litex/soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v @@ -39,13 +39,13 @@ // in a pipelined one. The multi-cycle multiplier stalls the pipe // for 32 cycles. If both options are disabled, multiply operations // are not supported. -//`define CFG_MC_MULTIPLY_ENABLED +`define CFG_MC_MULTIPLY_ENABLED //`define CFG_PL_MULTIPLY_ENABLED // Enable the multi-cycle divider. Stalls the pipe until the result // is ready after 32 cycles. If disabled, the divide operation is not // supported. -//`define CFG_MC_DIVIDE_ENABLED +`define CFG_MC_DIVIDE_ENABLED // diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py index 6ac138117..fb9560706 100644 --- a/litex/soc/integration/cpu_interface.py +++ b/litex/soc/integration/cpu_interface.py @@ -24,10 +24,7 @@ def get_cpu_mak(cpu, variant): if cpu == "lm32": assert not clang, "lm32 not supported with clang." triple = "lm32-elf" - if variant == "minimal": - cpuflags = "-mbarrel-shift-enabled -msign-extend-enabled" - else: - cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled" + cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled" clang = False elif cpu == "or1k": # Default to CLANG unless told otherwise