From dacec6aa8677c1e1eea123ddd421eec02a5923e2 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Fri, 12 Jul 2019 14:12:51 +0200 Subject: [PATCH] spi: change CSR to CSRStorage --- litex/soc/cores/spi.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) mode change 100644 => 100755 litex/soc/cores/spi.py diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py old mode 100644 new mode 100755 index bf12cd153..0ead8062e --- a/litex/soc/cores/spi.py +++ b/litex/soc/cores/spi.py @@ -26,7 +26,7 @@ class SPIMaster(Module, AutoCSR): pads = Record(self.pads_layout) self.pads = pads - self._control = CSR(16) + self._control = CSRStorage(16) self._status = CSRStatus(1) self._mosi = CSRStorage(data_width) self._miso = CSRStatus(data_width) @@ -47,8 +47,8 @@ class SPIMaster(Module, AutoCSR): done = Signal() # XFER start: initialize SPI XFER on SPI_CONTROL_START write and latch length - self.comb += start.eq(self._control.re & self._control.r[SPI_CONTROL_START]) - self.sync += If(self._control.re, length.eq(self._control.r[SPI_CONTROL_LENGTH:])) + self.comb += start.eq(self._control.re & self._control.storage[SPI_CONTROL_START]) + self.sync += If(self._control.re, length.eq(self._control.storage[SPI_CONTROL_LENGTH:])) # XFER done self.comb += self._status.status[SPI_STATUS_DONE].eq(done)