From 08779202f482e9dac94687c7dc1b628f46dde82d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 21 Sep 2021 08:18:03 +0200 Subject: [PATCH] build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap). --- litex/build/io.py | 26 +++++++++++++------------- litex/build/lattice/common.py | 6 +++--- litex/build/xilinx/common.py | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/litex/build/io.py b/litex/build/io.py index 1d1a59ab5..73ba48015 100644 --- a/litex/build/io.py +++ b/litex/build/io.py @@ -148,40 +148,40 @@ class DDROutput(Special): # DDR Tristate ------------------------------------------------------------------------------------- class InferedDDRTristate(Module): - def __init__(self, i1, i2, o1, o2, oe1, oe2, io, clk): + def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): _o = Signal() _oe = Signal() _i = Signal() - self.specials += DDROutput(i1, i2, _o, clk) + self.specials += DDROutput(o1, o2, _o, clk) self.specials += DDROutput(oe1, oe2, _oe, clk) - self.specials += DDRInput(_i, o1, o2, clk) + self.specials += DDRInput(_i, i1, i2, clk) self.specials += Tristate(io, _o, _oe, _i) class DDRTristate(Special): - def __init__(self, i1, i2, o1, o2, oe1, oe2, io, clk=ClockSignal()): + def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=ClockSignal()): Special.__init__(self) - self.i1 = i1 - self.i2 = i2 + self.io = io self.o1 = o1 self.o2 = o2 self.oe1 = oe1 self.oe2 = oe2 - self.io = io + self.i1 = i1 + self.i2 = i2 self.clk = clk def iter_expressions(self): - yield self, "io", SPECIAL_INOUT - yield self, "i1", SPECIAL_INPUT - yield self, "i2", SPECIAL_INPUT - yield self, "o1", SPECIAL_OUTPUT - yield self, "o2", SPECIAL_OUTPUT + yield self, "io", SPECIAL_INOUT + yield self, "o1", SPECIAL_INPUT + yield self, "o2", SPECIAL_INPUT yield self, "oe1", SPECIAL_INPUT yield self, "oe2", SPECIAL_INPUT + yield self, "i1", SPECIAL_OUTPUT + yield self, "i2", SPECIAL_OUTPUT yield self, "clk", SPECIAL_INPUT @staticmethod def lower(dr): - return InferedDDRTristate(dr.i1, dr.i2, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.io, dr.clk) + return InferedDDRTristate(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk) # Clock Reset Generator ---------------------------------------------------------------------------- diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py index d325c4f1c..d19152c0b 100644 --- a/litex/build/lattice/common.py +++ b/litex/build/lattice/common.py @@ -305,9 +305,9 @@ class LatticeNXDDRTristateImpl(Module): _o = Signal() _oe = Signal() _i = Signal() - self.specials += DDROutput(i1, i2, _o, clk) - self.specials += SDROutput(oe1|oe2, _oe, clk) - self.specials += DDRInput(_i, o1, o2, clk) + self.specials += DDROutput(o1, o2, _o, clk) + self.specials += SDROutput(oe1 | oe2, _oe, clk) + self.specials += DDRInput(_i, i1, i2, clk) self.specials += Tristate(io, _o, _oe, _i) _oe.attr.add("syn_useioff") diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index f16e3454a..71abafe24 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -159,9 +159,9 @@ class XilinxDDRTristateImpl(Module): _o = Signal() _oe_n = Signal() _i = Signal() - self.specials += DDROutput(i1, i2, _o, clk) + self.specials += DDROutput(o1, o2, _o, clk) self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk) - self.specials += DDRInput(_i, o1, o2, clk) + self.specials += DDRInput(_i, i1, i2, clk) self.specials += Instance("IOBUF", io_IO = io, o_O = _i,