From 08a9392c54525a8c5454a1a41e28c0e9f1d7b347 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 28 Oct 2021 14:34:52 +0200 Subject: [PATCH] fhdl/memory: Simplify Read Logic. --- litex/gen/fhdl/memory.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/litex/gen/fhdl/memory.py b/litex/gen/fhdl/memory.py index ca07b1f2a..19fd6793f 100644 --- a/litex/gen/fhdl/memory.py +++ b/litex/gen/fhdl/memory.py @@ -118,15 +118,14 @@ def memory_emit_verilog(memory, ns, add_data_file): if port.mode in [WRITE_FIRST]: rd = f"\t{gn(adr_regs[n])} <= {gn(port.adr)};\n" - # In Write-First/No Change mode: + # In Read-First/No Change mode: if port.mode in [READ_FIRST, NO_CHANGE]: - bassign = f"{gn(data_regs[n])} <= {gn(memory)} [{gn(port.adr)}];\n" - # Always Read in Read-First mode. - if port.mode == READ_FIRST: - rd = f"\t{bassign}" + rd = "" # Only Read in No-Change mode when no Write. - elif port.mode == NO_CHANGE: - rd = f"\tif (!{gn(port.we)})\n\t\t{bassign}" + if port.mode == NO_CHANGE: + rd += f"\tif (!{gn(port.we)})\n\t" + # Read-First/No-Change Read logic. + rd += f"\t{gn(data_regs[n])} <= {gn(memory)}[{gn(port.adr)}];\n" # Add Read-Enable Logic. if port.re is None: