diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0732829fe..35267b45d 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -6,6 +6,7 @@
 # This file is Copyright (c) 2019 Gabriel L. Somlo <somlo@cmu.edu>
 # SPDX-License-Identifier: BSD-2-Clause
 
+import os
 import sys
 import time
 import logging
@@ -1277,6 +1278,9 @@ class LiteXSoC(SoC):
 
         # USB ACM (with ValentyUSB core).
         elif uart_name in ["usb_acm"]:
+            # FIXME: do proper install of ValentyUSB.
+            os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
+            sys.path.append("valentyusb")
             import valentyusb.usbcore.io as usbio
             import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
             usb_pads  = self.platform.request("usb")