From 08ff00317851345c7486aa58d8d2f5d07c9c8522 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 9 Dec 2023 06:08:53 +0100 Subject: [PATCH] tools/litex_server.py: jtag/udp mode: add missing addr_width parameter --- litex/tools/litex_server.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/tools/litex_server.py b/litex/tools/litex_server.py index 9599a164b..6ca88c42f 100755 --- a/litex/tools/litex_server.py +++ b/litex/tools/litex_server.py @@ -231,7 +231,7 @@ def main(): jtag_uart = JTAGUART(config=args.jtag_config, chain=int(args.jtag_chain)) jtag_uart.open() print("[CommUART] port: JTAG / ", end="") - comm = CommUART(os.ttyname(jtag_uart.name), debug=args.debug) + comm = CommUART(os.ttyname(jtag_uart.name), debug=args.debug, addr_width=int(args.addr_width)) # UDP mode elif args.udp: @@ -250,7 +250,7 @@ def main(): exit() else: print("[CommUDP] ip: {} / port: {} / ".format(udp_ip, udp_port), end="") - comm = CommUDP(udp_ip, udp_port, debug=args.debug) + comm = CommUDP(udp_ip, udp_port, debug=args.debug, addr_width=int(args.addr_width)) # PCIe mode elif args.pcie: