From 09a3ce0ee5871588e0ba578d67b5e990da991588 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Mar 2020 18:56:58 +0100 Subject: [PATCH] integration/soc/add_uart: add Model/Sim. --- litex/soc/integration/soc.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 91d446028..53684fdf7 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -931,6 +931,13 @@ class LiteXSoC(SoC): elif name in ["crossover"]: self.submodules.uart = uart.UARTCrossover() + # Model/Sim + elif name in ["model", "sim"]: + self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial")) + self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy, + tx_fifo_depth = fifo_depth, + rx_fifo_depth = fifo_depth)) + # JTAG Atlantic elif name in ["jtag_atlantic"]: from litex.soc.cores.jtag import JTAGAtlantic