diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 64d892f87..bec4f81a0 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -108,8 +108,6 @@ class BaseSoC(SoCSDRAM):
 
         # sdram
         self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
-        self.add_constant("A7DDRPHY_BITSLIP", 3)
-        self.add_constant("A7DDRPHY_DELAY", 14)
         sdram_module = MT41K128M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index b389024b2..d9205476a 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -384,7 +384,7 @@ static void do_command(char *c)
 	else if(strcmp(token, "sdrrderr") == 0) sdrrderr(get_token(&c));
 	else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c));
 #ifdef CSR_DDRPHY_BASE
-#ifndef A7DDRPHY_BITSLIP
+#ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
 	else if(strcmp(token, "sdrwlon") == 0) sdrwlon();
 	else if(strcmp(token, "sdrwloff") == 0) sdrwloff();
 #endif
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index c833227db..e83483dbe 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -195,7 +195,14 @@ void sdrwr(char *startaddr)
 }
 
 #ifdef CSR_DDRPHY_BASE
-#ifndef A7DDRPHY_BITSLIP
+
+#ifdef KUSDDRPHY
+#define ERR_DDRPHY_DELAY 512
+#else
+#define ERR_DDRPHY_DELAY 32
+#endif
+
+#ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
 
 void sdrwlon(void)
 {
@@ -213,12 +220,6 @@ void sdrwloff(void)
 	ddrphy_wlevel_en_write(0);
 }
 
-#ifdef KUSDDRPHY
-#define ERR_DDRPHY_DELAY 512
-#else
-#define ERR_DDRPHY_DELAY 32
-#endif
-
 static int write_level(int *delay, int *high_skew)
 {
 	int i;
@@ -289,6 +290,8 @@ static int write_level(int *delay, int *high_skew)
 	return ok;
 }
 
+#endif /* CSR_DDRPHY_WLEVEL_EN_ADDR */
+
 static void read_bitslip(int *delay, int *high_skew)
 {
 	int bitslip_thr;
@@ -425,7 +428,6 @@ static void read_delays(void)
 
 	printf("completed\n");
 }
-#endif /* A7DDRPHY_BITSLIP */
 #endif /* CSR_DDRPHY_BASE */
 
 static unsigned int seed_to_data_32(unsigned int seed, int random)
@@ -596,40 +598,27 @@ int memtest(void)
 }
 
 #ifdef CSR_DDRPHY_BASE
-#ifdef A7DDRPHY_BITSLIP
-int sdrlevel(void)
-{
-	int bitslip, delay, module;
-	int i;
-	sdram_dfii_control_write(DFII_CONTROL_SEL);
-	for(module=0; module<8; module++) {
-		ddrphy_dly_sel_write(1<<module);
-		ddrphy_rdly_dq_rst_write(1);
-		for(bitslip=0; bitslip<A7DDRPHY_BITSLIP; bitslip++) {
-			// 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip
-			for(i=0; i<3; i++)
-				ddrphy_rdly_dq_bitslip_write(1);
-		}
-		for(delay=0; delay<A7DDRPHY_DELAY; delay++)
-			ddrphy_rdly_dq_inc_write(1);
-	}
-	return 1;
-}
-#else
 int sdrlevel(void)
 {
 	int delay[DFII_PIX_DATA_SIZE/2];
 	int high_skew[DFII_PIX_DATA_SIZE/2];
 
+#ifndef CSR_DDRPHY_WLEVEL_EN_ADDR
+	int i;
+	for(i=0; i<DFII_PIX_DATA_SIZE/2; i++) {
+		delay[i] = 0;
+		high_skew[i] = 0;
+	}
+#else
 	if(!write_level(delay, high_skew))
 		return 0;
+#endif
 	read_bitslip(delay, high_skew);
 	read_delays();
 
 	return 1;
 }
 #endif
-#endif
 
 int sdrinit(void)
 {