From 0a55ef5bc3e99f8f540bf98d8e139b245488b206 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 18 Sep 2015 11:07:14 +0800
Subject: [PATCH] test: add divider

---
 migen/test/test_divider.py | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 migen/test/test_divider.py

diff --git a/migen/test/test_divider.py b/migen/test/test_divider.py
new file mode 100644
index 000000000..5040d9965
--- /dev/null
+++ b/migen/test/test_divider.py
@@ -0,0 +1,26 @@
+import unittest
+
+from migen import *
+from migen.genlib.divider import Divider
+from migen.test.support import SimCase
+
+
+class DivisionCase(SimCase, unittest.TestCase):
+    class TestBench(Module):
+        def __init__(self):
+            self.submodules.dut = Divider(4)
+
+    def test_division(self):
+        def gen():
+            for dividend in range(16):
+                for divisor in range(1, 16):
+                    yield self.tb.dut.dividend_i, dividend
+                    yield self.tb.dut.divisor_i, divisor
+                    yield self.tb.dut.start_i, 1
+                    yield
+                    yield self.tb.dut.start_i, 0
+                    while not (yield self.tb.dut.ready_o):
+                        yield
+                    self.assertEqual((yield self.tb.dut.quotient_o), dividend//divisor)
+                    self.assertEqual((yield self.tb.dut.remainder_o), dividend%divisor)
+        self.run_with(gen())