diff --git a/litex/build/efinix/__init__.py b/litex/build/efinix/__init__.py
index c0efa1e9e..d7d7ee3c8 100644
--- a/litex/build/efinix/__init__.py
+++ b/litex/build/efinix/__init__.py
@@ -1,3 +1,4 @@
 from litex.build.efinix.programmer import EfinixProgrammer
 from litex.build.efinix.dbparser import EfinixDbParser
-from litex.build.efinix.ifacewriter import InterfaceWriter
\ No newline at end of file
+from litex.build.efinix.ifacewriter import InterfaceWriter
+from litex.build.efinix.platform import EfinixPlatform
\ No newline at end of file
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 22ecfab97..8075e00ff 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -364,6 +364,10 @@ class VexRiscvSMP(CPU):
         from litex.build.altera import AlteraPlatform
         if isinstance(platform, AlteraPlatform):
             ram_filename = "Ram_1w_1rs_Intel.v"
+        # On Efinix platforms, use specific implementation.
+        from litex.build.efinix import EfinixPlatform
+        if isinstance(platform, EfinixPlatform):
+            ram_filename = "Ram_1w_1rs_Efinix.v"
         platform.add_source(os.path.join(vdir, ram_filename), "verilog")
 
         # Add Cluster.