diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py
index 969109f6d..e45bf4400 100644
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@@ -182,13 +182,12 @@ class WishboneDMAWriter(Module, AutoCSR):
         self.submodules += fsm
         self.comb += fsm.reset.eq(~self._enable.storage)
         fsm.act("IDLE",
-            self.sink.ready.eq(1),
             NextValue(offset, 0),
             NextState("RUN"),
         )
         fsm.act("RUN",
             self._sink.valid.eq(self.sink.valid),
-            self._sink.last.eq(offset == (length - 1)),
+            self._sink.last.eq(self.sink.last | (offset + 1 == length)),
             self._sink.address.eq(base + offset),
             self._sink.data.eq(self.sink.data),
             self.sink.ready.eq(self._sink.ready),