From 6ad6d1e414c727f1beea0f256c0fdff7665e13a5 Mon Sep 17 00:00:00 2001 From: Vegard Storheil Eriksen Date: Sat, 10 Sep 2022 10:13:18 +0200 Subject: [PATCH 1/2] =?UTF-8?q?cores/dma:=20Don=E2=80=99t=20drop=20data=20?= =?UTF-8?q?while=20idle.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- litex/soc/cores/dma.py | 1 - 1 file changed, 1 deletion(-) diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py index 969109f6d..99b9b7dcc 100644 --- a/litex/soc/cores/dma.py +++ b/litex/soc/cores/dma.py @@ -182,7 +182,6 @@ class WishboneDMAWriter(Module, AutoCSR): self.submodules += fsm self.comb += fsm.reset.eq(~self._enable.storage) fsm.act("IDLE", - self.sink.ready.eq(1), NextValue(offset, 0), NextState("RUN"), ) From 3c4c12a72f7f36c6b662498bbfaa3cd483a341d8 Mon Sep 17 00:00:00 2001 From: Vegard Storheil Eriksen Date: Sat, 10 Sep 2022 10:15:23 +0200 Subject: [PATCH 2/2] cores/dma: End transfer when the last flag is set. --- litex/soc/cores/dma.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py index 99b9b7dcc..e45bf4400 100644 --- a/litex/soc/cores/dma.py +++ b/litex/soc/cores/dma.py @@ -187,7 +187,7 @@ class WishboneDMAWriter(Module, AutoCSR): ) fsm.act("RUN", self._sink.valid.eq(self.sink.valid), - self._sink.last.eq(offset == (length - 1)), + self._sink.last.eq(self.sink.last | (offset + 1 == length)), self._sink.address.eq(base + offset), self._sink.data.eq(self.sink.data), self.sink.ready.eq(self._sink.ready),