From 0b40d78b0d282440025721bf8951a042e038c598 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 26 Oct 2021 19:59:02 +0200 Subject: [PATCH] cores/jtag/ECP5JTAG: Delay TCK with LUT4 to avoid sys_clk/jtag_clk relationship and support higher jtag_clk frequencies. Tested succesfully on the ButterStick with 75MHz sys_clk/25MHz jtag_clk. Current tck_delay_luts is abritrary and should probably be adjusted. --- litex/soc/cores/jtag.py | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py index 08f4f16d7..e12de1ec9 100644 --- a/litex/soc/cores/jtag.py +++ b/litex/soc/cores/jtag.py @@ -90,7 +90,7 @@ class USJTAG(XilinxJTAG): # ECP5 JTAG ---------------------------------------------------------------------------------------- class ECP5JTAG(Module): - def __init__(self): + def __init__(self, tck_delay_luts=8): self.reset = Signal() self.capture = Signal() self.shift = Signal() @@ -122,9 +122,21 @@ class ECP5JTAG(Module): i_JTDO1 = self.tdo, # FF(negedge TCK, JTDO1) if (IR==0x32 && FSM==Shift-DR) ) - # Note due to TDI being registered inside JTAGG: - # We delay TCK here, so TDI is valid on our local TCK edge. - self.specials += MultiReg(tck, self.tck) + # TDI/TCK are synchronous on JTAGG output (TDI being registered with TCK). Introduce a delay + # on TCK with multiple LUT4s to allow its use as the JTAG Clk. + for i in range(tck_delay_luts): + new_tck = Signal() + self.specials += Instance("LUT4", + attr = {"keep"}, + p_INIT = 1, + i_A = tck, + i_B = 0, + i_C = 0, + i_D = 0, + o_Z = new_tck + ) + tck = new_tck + self.comb += self.tck.eq(tck) # JTAG PHY -----------------------------------------------------------------------------------------