From 0be607dad95582e902066b990aa11d69e9fb965e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Thu, 16 Jul 2020 10:26:12 +0200 Subject: [PATCH] soc/integration: revert `bus` argument for add_ram/add_rom --- litex/soc/integration/soc.py | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index d52402c95..aee695c10 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -753,28 +753,19 @@ class SoC(Module): setattr(self.submodules, name, SoCController(**kwargs)) self.csr.add(name, use_loc_if_exists=True) - def add_ram(self, name, origin, size, contents=[], mode="rw", bus=None): - if bus is None: - bus = wishbone.Interface(data_width=self.bus.data_width) - - if isinstance(bus, wishbone.Interface): - ram = wishbone.SRAM(size, bus=bus, init=contents, read_only=(mode == "r")) - elif isinstance(bus, axi.AXILiteInterface): - ram = axi.AXILiteSRAM(size, bus=bus, init=contents, read_only=(mode == "r")) - else: - raise TypeError(bus) - + def add_ram(self, name, origin, size, contents=[], mode="rw"): + ram_bus = wishbone.Interface(data_width=self.bus.data_width) + ram = wishbone.SRAM(size, bus=ram_bus, init=contents, read_only=(mode == "r")) self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode)) self.check_if_exists(name) - self.logger.info("{} RAM {} {} {}.".format( - colorer("Wishbone" if isinstance(bus, wishbone.Interface) else "AXILite"), + self.logger.info("RAM {} {} {}.".format( colorer(name), colorer("added", color="green"), self.bus.regions[name])) setattr(self.submodules, name, ram) - def add_rom(self, name, origin, size, contents=[], bus=None): - self.add_ram(name, origin, size, contents, mode="r", bus=bus) + def add_rom(self, name, origin, size, contents=[]): + self.add_ram(name, origin, size, contents, mode="r") def add_csr_bridge(self, origin): self.submodules.csr_bridge = wishbone.Wishbone2CSR(