From 0caac2246d180bd73ac520c9a46e84a2810ba1f4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 24 Feb 2013 13:07:25 +0100 Subject: [PATCH] Use new 'specials' API --- milkymist/framebuffer/__init__.py | 3 ++- milkymist/lm32/__init__.py | 3 ++- milkymist/m1crg/__init__.py | 3 ++- milkymist/minimac3/__init__.py | 7 +++---- milkymist/s6ddrphy/__init__.py | 3 ++- 5 files changed, 11 insertions(+), 8 deletions(-) diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py index d0dea5fa6..4106ce8cd 100644 --- a/milkymist/framebuffer/__init__.py +++ b/milkymist/framebuffer/__init__.py @@ -1,4 +1,5 @@ from migen.fhdl.structure import * +from migen.fhdl.specials import Instance from migen.flow.actor import * from migen.flow.network import * from migen.flow.transactions import * @@ -155,7 +156,7 @@ class FIFO(Actor): self.busy.eq(0) ], - instances=[asfifo]) + specials={asfifo}) def sim_fifo_gen(): while True: diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py index cc2c6ed72..e2c743f98 100644 --- a/milkymist/lm32/__init__.py +++ b/milkymist/lm32/__init__.py @@ -1,4 +1,5 @@ from migen.fhdl.structure import * +from migen.fhdl.specials import Instance from migen.bus import wishbone class LM32: @@ -49,4 +50,4 @@ class LM32: self.ibus.adr.eq(self._i_adr_o[2:]), self.dbus.adr.eq(self._d_adr_o[2:]) ] - return Fragment(comb=comb, instances=[self._inst]) + return Fragment(comb, specials={self._inst}) diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py index cd8a78f6d..baef94975 100644 --- a/milkymist/m1crg/__init__.py +++ b/milkymist/m1crg/__init__.py @@ -1,6 +1,7 @@ from fractions import Fraction from migen.fhdl.structure import * +from migen.fhdl.specials import Instance from mibuild.crg import CRG class M1CRG(CRG): @@ -58,4 +59,4 @@ class M1CRG(CRG): self._inst = Instance("m1crg", *inst_items) def get_fragment(self): - return Fragment(instances=[self._inst]) + return Fragment(specials={self._inst}) diff --git a/milkymist/minimac3/__init__.py b/milkymist/minimac3/__init__.py index dff85a513..8c8d68d40 100644 --- a/milkymist/minimac3/__init__.py +++ b/milkymist/minimac3/__init__.py @@ -1,4 +1,5 @@ from migen.fhdl.structure import * +from migen.fhdl.specials import Instance from migen.bank.description import * from migen.bank.eventmanager import * from migen.bank import csrgen @@ -59,8 +60,7 @@ class MiniMAC: rx_pending_0_r.eq(rx_pending_0), rx_pending_1_r.eq(rx_pending_1) ] - inst = [ - Instance("minimac3", + inst = Instance("minimac3", Instance.ClockPort("sys_clk"), Instance.ResetPort("sys_rst"), @@ -94,7 +94,6 @@ class MiniMAC: Instance.Input("phy_rx_er", self.phy_rx_er), Instance.Input("phy_col", self.phy_col), Instance.Input("phy_crs", self.phy_crs)) - ] - return Fragment(comb, sync, instances=inst) \ + return Fragment(comb, sync, specials={inst}) \ + self.events.get_fragment() \ + self.bank.get_fragment() diff --git a/milkymist/s6ddrphy/__init__.py b/milkymist/s6ddrphy/__init__.py index 882af43d3..3f16baf1f 100644 --- a/milkymist/s6ddrphy/__init__.py +++ b/milkymist/s6ddrphy/__init__.py @@ -1,4 +1,5 @@ from migen.fhdl.structure import * +from migen.fhdl.specials import Instance from migen.bus import dfi class S6DDRPHY: @@ -41,4 +42,4 @@ class S6DDRPHY: self._inst = Instance("s6ddrphy", *inst_items) def get_fragment(self): - return Fragment(instances=[self._inst]) + return Fragment(specials={self._inst})