diff --git a/doc/migen.txt b/doc/migen.txt
index 18bbdbc01..54a2e1f46 100644
--- a/doc/migen.txt
+++ b/doc/migen.txt
@@ -310,7 +310,7 @@ Each port description contains:
     in each sub-word. If it is set to 0, the port is using whole-word
     writes only and the width of the write enable signal must be 1. This
     parameter is ignored if there is no write enable signal.
-  - the mode of the port (default READ_FIRST, ignored for asynchronous
+  - the mode of the port (default WRITE_FIRST, ignored for asynchronous
     ports). It can be:
      * READ_FIRST: during a write, the previous value is read.
      * WRITE_FIRST: the written value is returned.
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index c953834d1..4c0ef34bf 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -232,7 +232,7 @@ class Instance:
 
 class MemoryPort:
 	def __init__(self, adr, dat_r, we=None, dat_w=None,
-	  async_read=False, re=None, we_granularity=0, mode=READ_FIRST):
+	  async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST):
 		self.adr = adr
 		self.dat_r = dat_r
 		self.we = we