From 0daeff86896c1951c8737caa25e870eeca8713e2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 25 Apr 2017 10:56:19 +0200
Subject: [PATCH] gen/sim/core: do not use reset_less clock_domains for the one
 that are created (logic may need to access reset signal)

---
 litex/gen/sim/core.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/litex/gen/sim/core.py b/litex/gen/sim/core.py
index c23c2a65d..8b03a0dfd 100644
--- a/litex/gen/sim/core.py
+++ b/litex/gen/sim/core.py
@@ -41,7 +41,7 @@ class TimeManager:
             else:
                 high = False
             self.clocks[k] = ClockState(high, half_period, half_period - phase)
-    
+
     def tick(self):
         rising = set()
         falling = set()
@@ -64,14 +64,14 @@ str2op = {
     "+": operator.add,
     "-": operator.sub,
     "*": operator.mul,
-    
+
     ">>>": operator.rshift,
     "<<<": operator.lshift,
-    
+
     "&": operator.and_,
     "^": operator.xor,
     "|": operator.or_,
-    
+
     "<": operator.lt,
     "<=": operator.le,
     "==": operator.eq,
@@ -271,7 +271,7 @@ class Simulator:
         self.time = TimeManager(clocks)
         for clock in clocks.keys():
             if clock not in self.fragment.clock_domains:
-                cd = ClockDomain(name=clock, reset_less=True)
+                cd = ClockDomain(name=clock)
                 cd.clk.reset = C(self.time.clocks[clock].high)
                 self.fragment.clock_domains.append(cd)