From 0e68daebf3210bded0754bc30ec42b4935992b95 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 13 Sep 2018 05:31:35 +0200 Subject: [PATCH] targets: self.pll_sys --> pll_sys --- litex/boards/targets/arty.py | 6 +++--- litex/boards/targets/genesys2.py | 6 +++--- litex/boards/targets/kc705.py | 6 +++--- litex/boards/targets/nexys4ddr.py | 6 +++--- litex/boards/targets/nexys_video.py | 6 +++--- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index fcb2a4f6e..aeda2f901 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -31,7 +31,7 @@ class _CRG(Module): pll_locked = Signal() pll_fb = Signal() - self.pll_sys = Signal() + pll_sys = Signal() pll_sys4x = Signal() pll_sys4x_dqs = Signal() pll_clk200 = Signal() @@ -47,7 +47,7 @@ class _CRG(Module): # 100 MHz p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=self.pll_sys, + o_CLKOUT0=pll_sys, # 400 MHz p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0, @@ -65,7 +65,7 @@ class _CRG(Module): p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0, o_CLKOUT4=pll_clk50 ), - Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 460f0e47f..5702a5e23 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -32,7 +32,7 @@ class _CRG(Module): pll_locked = Signal() pll_fb = Signal() - self.pll_sys = Signal() + pll_sys = Signal() pll_sys4x = Signal() pll_clk200 = Signal() self.specials += [ @@ -46,7 +46,7 @@ class _CRG(Module): # 125MHz p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=self.pll_sys, + o_CLKOUT0=pll_sys, # 500MHz p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, @@ -56,7 +56,7 @@ class _CRG(Module): p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200 ), - Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst_n), diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 514c33e84..c2d2553d6 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -32,7 +32,7 @@ class _CRG(Module): pll_locked = Signal() pll_fb = Signal() - self.pll_sys = Signal() + pll_sys = Signal() pll_sys4x = Signal() pll_clk200 = Signal() self.specials += [ @@ -46,7 +46,7 @@ class _CRG(Module): # 125MHz p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=self.pll_sys, + o_CLKOUT0=pll_sys, # 500MHz p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, @@ -56,7 +56,7 @@ class _CRG(Module): p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200 ), - Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst), diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 1b6ff7164..fb1e2e2d1 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -28,7 +28,7 @@ class _CRG(Module): pll_locked = Signal() pll_fb = Signal() - self.pll_sys = Signal() + pll_sys = Signal() pll_sys2x = Signal() pll_sys2x_dqs = Signal() pll_clk200 = Signal() @@ -43,7 +43,7 @@ class _CRG(Module): # 100 MHz p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=self.pll_sys, + o_CLKOUT0=pll_sys, # 200 MHz p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, @@ -57,7 +57,7 @@ class _CRG(Module): p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=pll_clk200 ), - Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys2x, o_O=self.cd_sys2x.clk), Instance("BUFG", i_I=pll_sys2x_dqs, o_O=self.cd_sys2x_dqs.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 3a97e2aac..1af07c7f8 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -31,7 +31,7 @@ class _CRG(Module): pll_locked = Signal() pll_fb = Signal() - self.pll_sys = Signal() + pll_sys = Signal() pll_sys4x = Signal() pll_sys4x_dqs = Signal() pll_clk200 = Signal() @@ -46,7 +46,7 @@ class _CRG(Module): # 100 MHz p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=self.pll_sys, + o_CLKOUT0=pll_sys, # 400 MHz p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0, @@ -60,7 +60,7 @@ class _CRG(Module): p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=pll_clk200 ), - Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),