diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 076934dd2..48009791b 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -541,7 +541,8 @@ class SoCCore(Module):
             alignment=self.csr_alignment)
 
         # Add CSRs interconnect
-        self.submodules.csrcon = csr_bus.InterconnectShared(
+        if len(self._csr_masters) != 0:
+            self.submodules.csrcon = csr_bus.InterconnectShared(
                 self._csr_masters, self.csrbankarray.get_buses())
 
         # Check and add CSRs regions
diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 54a3db536..d6a72e502 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -121,7 +121,8 @@ class SoCSDRAM(SoCCore):
                 raise FinalizeError("Need to call SoCSDRAM.register_sdram()")
 
             # Arbitrate wishbone interfaces to the DRAM
-            self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram)
+            if len(self._wb_sdram_ifs) != 0:
+                self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram)
         SoCCore.do_finalize(self)