From 0ea7a1fd05182bd7c6ecb4e1ebc7ae3b5e949750 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Sep 2019 08:40:22 +0200 Subject: [PATCH] soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty For example a standalone controller with no exposed CSRs (probably not a very useful configuration but I really don't like python backtraces) Signed-off-by: Benjamin Herrenschmidt --- litex/soc/integration/soc_core.py | 3 ++- litex/soc/integration/soc_sdram.py | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 076934dd2..48009791b 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -541,7 +541,8 @@ class SoCCore(Module): alignment=self.csr_alignment) # Add CSRs interconnect - self.submodules.csrcon = csr_bus.InterconnectShared( + if len(self._csr_masters) != 0: + self.submodules.csrcon = csr_bus.InterconnectShared( self._csr_masters, self.csrbankarray.get_buses()) # Check and add CSRs regions diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 54a3db536..d6a72e502 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -121,7 +121,8 @@ class SoCSDRAM(SoCCore): raise FinalizeError("Need to call SoCSDRAM.register_sdram()") # Arbitrate wishbone interfaces to the DRAM - self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram) + if len(self._wb_sdram_ifs) != 0: + self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram) SoCCore.do_finalize(self)