diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py
index 5712b5547..969109f6d 100644
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@@ -1,7 +1,7 @@
 #
 # This file is part of LiteX.
 #
-# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2020-2021 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
 """Direct Memory Access (DMA) reader and writer modules."""
@@ -74,12 +74,12 @@ class WishboneDMAReader(Module, AutoCSR):
         if with_csr:
             self.add_csr()
 
-    def add_csr(self):
-        self._base   = CSRStorage(64)
-        self._length = CSRStorage(32)
-        self._enable = CSRStorage()
+    def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
+        self._base   = CSRStorage(64, reset=default_base)
+        self._length = CSRStorage(32, reset=default_length)
+        self._enable = CSRStorage(reset=default_enable)
         self._done   = CSRStatus()
-        self._loop   = CSRStorage()
+        self._loop   = CSRStorage(reset=default_loop)
         self._offset = CSRStatus(32)
 
         # # #
@@ -116,9 +116,7 @@ class WishboneDMAReader(Module, AutoCSR):
                 )
             )
         )
-        fsm.act("DONE",
-            self._done.status.eq(1)
-        )
+        fsm.act("DONE", self._done.status.eq(1))
 
 # WishboneDMAWriter --------------------------------------------------------------------------------
 
@@ -157,15 +155,16 @@ class WishboneDMAWriter(Module, AutoCSR):
         if with_csr:
             self.add_csr()
 
-    def add_csr(self):
+    def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
         self._sink = self.sink
         self.sink  = stream.Endpoint([("data", self.bus.data_width)])
 
-        self._base   = CSRStorage(64)
-        self._length = CSRStorage(32)
-        self._enable = CSRStorage()
+        self._base   = CSRStorage(64, reset=default_base)
+        self._length = CSRStorage(32, reset=default_length)
+        self._enable = CSRStorage(reset=default_enable)
         self._done   = CSRStatus()
-        self._loop   = CSRStorage()
+        self._loop   = CSRStorage(reset=default_loop)
+        self._offset = CSRStatus(32)
 
         # # #
 
@@ -176,6 +175,8 @@ class WishboneDMAWriter(Module, AutoCSR):
         self.comb += base.eq(self._base.storage[shift:])
         self.comb += length.eq(self._length.storage[shift:])
 
+        self.comb += self._offset.status.eq(offset)
+
         fsm = FSM(reset_state="IDLE")
         fsm = ResetInserter()(fsm)
         self.submodules += fsm
@@ -187,12 +188,13 @@ class WishboneDMAWriter(Module, AutoCSR):
         )
         fsm.act("RUN",
             self._sink.valid.eq(self.sink.valid),
-            self._sink.data.eq(self.sink.data),
+            self._sink.last.eq(offset == (length - 1)),
             self._sink.address.eq(base + offset),
+            self._sink.data.eq(self.sink.data),
             self.sink.ready.eq(self._sink.ready),
             If(self.sink.valid & self.sink.ready,
                 NextValue(offset, offset + 1),
-                If(offset == (length - 1),
+                If(self._sink.last,
                     If(self._loop.storage,
                         NextValue(offset, 0)
                     ).Else(
@@ -201,6 +203,4 @@ class WishboneDMAWriter(Module, AutoCSR):
                 )
             )
         )
-        fsm.act("DONE",
-            self._done.status.eq(1)
-        )
+        fsm.act("DONE", self._done.status.eq(1))