From 0eff65bb3124f569f0d7be827b7fe543c4d3ad5b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 22 Jul 2019 07:55:47 +0200 Subject: [PATCH] cores/up5ksram: optimize bus.adr decoding --- litex/soc/cores/up5kspram.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/up5kspram.py b/litex/soc/cores/up5kspram.py index 4a790d189..805801691 100644 --- a/litex/soc/cores/up5kspram.py +++ b/litex/soc/cores/up5kspram.py @@ -47,7 +47,7 @@ class Up5kSPRAM(Module): wren = Signal() self.comb += [ datain.eq(self.bus.dat_w[16*w:16*(w+1)]), - If(self.bus.adr[14:16] == d, + If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d, wren.eq(self.bus.we & self.bus.stb & self.bus.cyc), self.bus.dat_r[16*w:16*(w+1)].eq(dataout) ),