From 0f097fd4c7af5e6c8420b2f347850367ca136f21 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 1 Nov 2022 16:10:46 +0800 Subject: [PATCH] cpu/openc906: misc fixes/enhancements related to L1$ Currently L1$ flush code does not work well because of lack of synchorizing. Switch to use T-Head extended instructions instead of CSRs to flush L1 cache (both D and I), and THEADISAEE is set for this. In addition, Some other performance-related options are enabled too, including branch predicting, cache prefetching, etc. Signed-off-by: Icenowy Zheng --- litex/soc/cores/cpu/openc906/crt0.S | 8 ++++++-- litex/soc/cores/cpu/openc906/system.h | 8 ++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/cpu/openc906/crt0.S b/litex/soc/cores/cpu/openc906/crt0.S index 4993d5510..c4cb80e83 100644 --- a/litex/soc/cores/cpu/openc906/crt0.S +++ b/litex/soc/cores/cpu/openc906/crt0.S @@ -56,8 +56,12 @@ crt_init: la sp, _fstack la t0, trap_entry csrw mtvec, t0 - li t0, 0x3 - csrs 0x7c1, t0 // enable L1I+L1D + li t0, 0x400000 + csrs 0x7c0, t0 // enable THEADISAEE + li t0, 0x73 + csrs 0x7c1, t0 // enable L1$ (I+D) + Branch Prediction + Return Stack + li t0, 0x504 + csrs 0x7c5, t0 // enable L1$ prefetching data_init: la t0, _fdata diff --git a/litex/soc/cores/cpu/openc906/system.h b/litex/soc/cores/cpu/openc906/system.h index ae113b0cc..242dea727 100644 --- a/litex/soc/cores/cpu/openc906/system.h +++ b/litex/soc/cores/cpu/openc906/system.h @@ -35,13 +35,13 @@ void busy_wait_us(unsigned int us); asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) __attribute__((unused)) static void flush_cpu_icache(void) { - csrc(0x7c2, 0x33); - csrs(0x7c2, 0x11); + asm volatile (".long 0x0100000b"); /* icache.iall */ + asm volatile (".long 0x01a0000b"); /* sync.i */ }; __attribute__((unused)) static void flush_cpu_dcache(void) { - csrc(0x7c2, 0x33); - csrs(0x7c2, 0x12); + asm volatile (".long 0x0030000b"); /* dcache.ciall */ + asm volatile (".long 0x01a0000b"); /* sync.i */ }; #ifdef __cplusplus