diff --git a/CHANGES.md b/CHANGES.md
index ee72b1eaf..74346a571 100644
--- a/CHANGES.md
+++ b/CHANGES.md
@@ -47,6 +47,7 @@
 	- litepcie/frontend/dma        : Added optional integrated data-width converter and data_width parameters to simplify integration/user logic.
 	- soc/add_uartbone/sata/sdcard : Added support for multiple instances in gateware as for the other cores.
 	- liteeth_gen                  : Added raw UDP port support.
+	- build/vivado                 : Added .dcp generation also after synthesis and placement.
 
 	[> Changed
 	----------
diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 073dacd31..9b51b65ad 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -298,6 +298,7 @@ class XilinxVivadoToolchain(GenericToolchain):
         tcl.append(f"report_timing_summary -file {self._build_name}_timing_synth.rpt")
         tcl.append(f"report_utilization -hierarchical -file {self._build_name}_utilization_hierarchical_synth.rpt")
         tcl.append(f"report_utilization -file {self._build_name}_utilization_synth.rpt")
+        tcl.append(f"write_checkpoint -force {self._build_name}_synth.dcp")
 
         # Optimize
         tcl.append("\n# Optimize design\n")
@@ -323,6 +324,7 @@ class XilinxVivadoToolchain(GenericToolchain):
         tcl.append(f"report_io -file {self._build_name}_io.rpt")
         tcl.append(f"report_control_sets -verbose -file {self._build_name}_control_sets.rpt")
         tcl.append(f"report_clock_utilization -file {self._build_name}_clock_utilization.rpt")
+        tcl.append(f"write_checkpoint -force {self._build_name}_place.dcp")
 
         # Add pre-routing commands
         tcl.append("\n# Add pre-routing commands\n")