From 0f352cd6481f64b2cacfd63a4bcf08a4ce15315b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 6 Apr 2020 13:16:13 +0200 Subject: [PATCH] soc/cores: use reset_less on datapath/configuration CSRStorages. --- litex/soc/cores/clock.py | 4 ++-- litex/soc/cores/icap.py | 6 +++--- litex/soc/cores/pwm.py | 8 ++++---- litex/soc/cores/spi.py | 2 +- litex/soc/cores/spi_flash.py | 4 ++-- litex/soc/cores/xadc.py | 4 ++-- 6 files changed, 14 insertions(+), 14 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 3fdd1ce99..d264e201e 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -157,8 +157,8 @@ class XilinxClocking(Module, AutoCSR): self.drp_read = CSR() self.drp_write = CSR() self.drp_drdy = CSRStatus() - self.drp_adr = CSRStorage(7) - self.drp_dat_w = CSRStorage(16) + self.drp_adr = CSRStorage(7, reset_less=True) + self.drp_dat_w = CSRStorage(16, reset_less=True) self.drp_dat_r = CSRStatus(16) # # # diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py index 3add30122..6451529ac 100644 --- a/litex/soc/cores/icap.py +++ b/litex/soc/cores/icap.py @@ -18,8 +18,8 @@ class ICAP(Module, AutoCSR): reloaded from SPI Flash by writing 0x00000000 at address @0x4. """ def __init__(self, simulation=False): - self.addr = CSRStorage(5, description="ICAP Write Address.") - self.data = CSRStorage(32, description="ICAP Write Data.") + self.addr = CSRStorage(5, reset_less=True, description="ICAP Write Address.") + self.data = CSRStorage(32, reset_less=True, description="ICAP Write Data.") self.send = CSRStorage(description="ICAP Control.\n\n Write ``1`` send a write command to the ICAP.") self.done = CSRStatus(reset=1, description="ICAP Status.\n\n Write command done when read as ``1``.") @@ -91,7 +91,7 @@ class ICAPBitstream(Module, AutoCSR): the ICAPE2. """ def __init__(self, fifo_depth=8, icap_clk_div=4, simulation=False): - self.sink_data = CSRStorage(32) + self.sink_data = CSRStorage(32, reset_less=True) self.sink_ready = CSRStatus() # # # diff --git a/litex/soc/cores/pwm.py b/litex/soc/cores/pwm.py index 3adc0ca2f..83ece092b 100644 --- a/litex/soc/cores/pwm.py +++ b/litex/soc/cores/pwm.py @@ -25,7 +25,7 @@ class PWM(Module, AutoCSR): # # # - counter = Signal(32) + counter = Signal(32, reset_less=True) sync = getattr(self.sync, clock_domain) sync += [ @@ -36,7 +36,7 @@ class PWM(Module, AutoCSR): ).Else( pwm.eq(0) ), - If(counter == (self.period - 1), + If(counter >= (self.period - 1), counter.eq(0) ) ).Else( @@ -51,10 +51,10 @@ class PWM(Module, AutoCSR): def add_csr(self, clock_domain): self._enable = CSRStorage(description="""PWM Enable.\n Write ``1`` to enable PWM.""") - self._width = CSRStorage(32, description="""PWM Width.\n + self._width = CSRStorage(32, reset_less=True, description="""PWM Width.\n Defines the *Duty cycle* of the PWM. PWM is active high for *Width* ``{cd}_clk`` cycles and active low for *Period - Width* ``{cd}_clk`` cycles.""".format(cd=clock_domain)) - self._period = CSRStorage(32, description="""PWM Period.\n + self._period = CSRStorage(32, reset_less=True, description="""PWM Period.\n Defines the *Period* of the PWM in ``{cd}_clk`` cycles.""".format(cd=clock_domain)) n = 0 if clock_domain == "sys" else 2 diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py index afa0b9506..8cf7ceb50 100644 --- a/litex/soc/cores/spi.py +++ b/litex/soc/cores/spi.py @@ -131,7 +131,7 @@ class SPIMaster(Module, AutoCSR): self._status = CSRStatus(fields=[ CSRField("done", size=1, offset=0, description="SPI Xfer done when read as ``1``.") ], description="SPI Status.") - self._mosi = CSRStorage(self.data_width, description="SPI MOSI data (MSB-first serialization).") + self._mosi = CSRStorage(self.data_width, reset_less=True, description="SPI MOSI data (MSB-first serialization).") self._miso = CSRStatus(self.data_width, description="SPI MISO data (MSB-first de-serialization).") self._cs = CSRStorage(fields=[ CSRField("sel", len(self.cs), reset=1, description="Write ``1`` to corresponding bit to enable Xfer for chip.") diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index 906ffb136..c3066b38c 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -88,7 +88,7 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR): assert spi_width >= 2 if with_bitbang: - self.bitbang = CSRStorage(4, fields=[ + self.bitbang = CSRStorage(4, reset_less=True, fields=[ CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."), CSRField("clk", description="Output value for SPI CLK pin."), CSRField("cs_n", description="Output value for SPI CSn pin."), @@ -229,7 +229,7 @@ class SpiFlashSingle(SpiFlashCommon, AutoCSR): self.bus = bus = wishbone.Interface() if with_bitbang: - self.bitbang = CSRStorage(4, fields=[ + self.bitbang = CSRStorage(4, reset_less=True, fields=[ CSRField("mosi", description="Output value for SPI MOSI pin."), CSRField("clk", description="Output value for SPI CLK pin."), CSRField("cs_n", description="Output value for SPI CSn pin."), diff --git a/litex/soc/cores/xadc.py b/litex/soc/cores/xadc.py index 984fc47dd..429f81686 100644 --- a/litex/soc/cores/xadc.py +++ b/litex/soc/cores/xadc.py @@ -114,8 +114,8 @@ class XADC(Module, AutoCSR): self.drp_read = CSR() self.drp_write = CSR() self.drp_drdy = CSRStatus() - self.drp_adr = CSRStorage(7) - self.drp_dat_w = CSRStorage(16) + self.drp_adr = CSRStorage(7, reset_less=True) + self.drp_dat_w = CSRStorage(16, reset_less=True) self.drp_dat_r = CSRStatus(16) # # #