From 0f9b0c6f0fbd43db4dd426bfbf3e9f5403393512 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2015 18:52:10 +0100 Subject: [PATCH] sdram/module: add MT47H128M8 DDR2 (used for a customer) --- misoclib/mem/sdram/module.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py index e41bced06..d105adb8a 100644 --- a/misoclib/mem/sdram/module.py +++ b/misoclib/mem/sdram/module.py @@ -138,6 +138,23 @@ class MT46H32M16(SDRAMModule): self.timing_settings) # DDR2 +class MT47H128M8(SDRAMModule): + geom_settings = { + "nbanks": 8, + "nrows": 16384, + "ncols": 1024 + } + timing_settings = { + "tRP": 15, + "tRCD": 15, + "tWR": 15, + "tWTR": 2, + "tREFI": 7800, + "tRFC": 127.5 + } + def __init__(self, clk_freq): + SDRAMModule.__init__(self, clk_freq, self.geom_settings, + self.timing_settings) # DDR3 class MT8JTF12864(SDRAMModule):