diff --git a/verilog/lm32/lm32_dp_ram.v b/verilog/lm32/lm32_dp_ram.v
index 1d7f4f170..6ef952aba 100644
--- a/verilog/lm32/lm32_dp_ram.v
+++ b/verilog/lm32/lm32_dp_ram.v
@@ -19,15 +19,15 @@ input [data_width-1:0] wdata_i;
 input [addr_width-1:0] raddr_i;
 output [data_width-1:0] rdata_o;
 
-reg [data_width-1:0] ram[addr_depth-1:0];
+reg [data_width-1:0] mem[addr_depth-1:0];
 
 reg [addr_width-1:0] raddr_r;
-assign rdata_o = ram[raddr_r];
+assign rdata_o = mem[raddr_r];
 
 always @ (posedge clk_i)
 begin
 	if (we_i)
-		ram[waddr_i] <= wdata_i;
+		mem[waddr_i] <= wdata_i;
 	raddr_r <= raddr_i;
 end