From 10eff37b84fe72fb2f94b26a9818cd0729bca4b8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Mar 2021 18:24:55 +0100 Subject: [PATCH] interconnect/axi: Fix AXILiteDownverterWrite/Read base address. Downconverter should start on master's addr, not on aligned master's addr. --- litex/soc/interconnect/axi.py | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 619ca76b3..637c954de 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -833,24 +833,18 @@ class _AXILiteDownConverterWrite(Module): dw_from = len(master.w.data) dw_to = len(slave.w.data) ratio = dw_from//dw_to - master_align = log2_int(master.data_width//8) - slave_align = log2_int(slave.data_width//8) skip = Signal() counter = Signal(max=ratio) aw_ready = Signal() w_ready = Signal() resp = Signal.like(master.b.resp) - addr_counter = Signal(master_align) # # # - # Slave address counter - self.comb += addr_counter[slave_align:].eq(counter) - # Data path self.comb += [ - slave.aw.addr.eq(Cat(addr_counter, master.aw.addr[master_align:])), + slave.aw.addr.eq(master.aw.addr + counter*(dw_to//8)), Case(counter, {i: slave.w.data.eq(master.w.data[i*dw_to:]) for i in range(ratio)}), Case(counter, {i: slave.w.strb.eq(master.w.strb[i*dw_to//8:]) for i in range(ratio)}), master.b.resp.eq(resp), @@ -930,19 +924,13 @@ class _AXILiteDownConverterRead(Module): dw_from = len(master.r.data) dw_to = len(slave.r.data) ratio = dw_from//dw_to - master_align = log2_int(master.data_width//8) - slave_align = log2_int(slave.data_width//8) skip = Signal() counter = Signal(max=ratio) resp = Signal.like(master.r.resp) - addr_counter = Signal(master_align) # # # - # Slave address counter - self.comb += addr_counter[slave_align:].eq(counter) - # Data path # Shift the data word r_data = Signal(dw_from, reset_less=True) @@ -950,7 +938,7 @@ class _AXILiteDownConverterRead(Module): self.comb += master.r.data.eq(Cat(r_data[dw_to:], slave.r.data)) # Connect address, resp self.comb += [ - slave.ar.addr.eq(Cat(addr_counter, master.ar.addr[master_align:])), + slave.ar.addr.eq(master.ar.addr + counter*(dw_to//8)), master.r.resp.eq(resp), ]