From 114890ee80bbcb3caf6ea98e9db66a1e8506f30d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 1 Sep 2014 23:11:15 +0200
Subject: [PATCH] sdramphy/initsequence: clean up mr1/mr2 computation on DDR3
 and enable Dynamic ODT

---
 misoclib/sdramphy/initsequence.py | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/misoclib/sdramphy/initsequence.py b/misoclib/sdramphy/initsequence.py
index af68aa197..54f734319 100644
--- a/misoclib/sdramphy/initsequence.py
+++ b/misoclib/sdramphy/initsequence.py
@@ -191,9 +191,22 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
 			mr0 |= wr_to_mr0[wr] << 9
 			return mr0
 
+		def format_mr1(output_drive_strength, rtt_nom):
+			mr1 = ((output_drive_strength >> 0) & 1) << 1
+			mr1 |= ((output_drive_strength >> 1) & 1) << 5
+			mr1 |= ((rtt_nom >> 0) & 1) << 2
+			mr1 |= ((rtt_nom >> 1) & 1) << 6
+			mr1 |= ((rtt_nom >> 2) & 1) << 9
+			return mr1
+
+		def format_mr2(cwl, rtt_wr):
+			mr2 = (cwl-5) << 3
+			mr2 |= rtt_wr << 9
+			return mr2
+
 		mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
-		mr1 = 6 # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
-		mr2 = (sdram_phy.phy_settings.cwl-5) << 3
+		mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
+		mr2 = format_mr2(sdram_phy.phy_settings.cwl, 2) # Rtt(WR) RZQ/4
 		mr3 = 0
 
 		init_sequence = [