From 116c2f15494af7cd51af74569f122ee245fd6eb4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 23 Apr 2021 16:16:31 +0200 Subject: [PATCH] cores/cpu: Cosmetic cleanups. --- litex/soc/cores/cpu/blackparrot/core.py | 21 +++- litex/soc/cores/cpu/cv32e40p/core.py | 67 +++++++++--- litex/soc/cores/cpu/ibex/core.py | 29 ++++-- litex/soc/cores/cpu/lm32/core.py | 73 ++++++------- litex/soc/cores/cpu/microwatt/core.py | 127 ++++++++++++----------- litex/soc/cores/cpu/minerva/core.py | 81 +++++++-------- litex/soc/cores/cpu/mor1kx/core.py | 124 +++++++++++----------- litex/soc/cores/cpu/picorv32/core.py | 42 ++++---- litex/soc/cores/cpu/rocket/core.py | 82 ++++++++------- litex/soc/cores/cpu/serv/core.py | 19 ++-- litex/soc/cores/cpu/vexriscv/core.py | 82 ++++++++------- litex/soc/cores/cpu/vexriscv_smp/core.py | 92 +++++++++------- litex/soc/cores/cpu/zynq7000/core.py | 101 +++++++++--------- 13 files changed, 522 insertions(+), 418 deletions(-) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 0ab7d4c01..ae5db539e 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -37,13 +37,22 @@ from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64 +class Open(Signal): pass + + +# Variants ----------------------------------------------------------------------------------------- + CPU_VARIANTS = ["standard", "sim"] +# GCC Flags ---------------------------------------------------------------------------------------- + GCC_FLAGS = { "standard": "-march=rv64ima -mabi=lp64 ", "sim": "-march=rv64ima -mabi=lp64 ", } +# BlackParrotRV64 ---------------------------------------------------------------------------------- + class BlackParrotRV64(CPU): name = "blackparrot" human_name = "BlackParrotRV64[ima]" @@ -53,8 +62,9 @@ class BlackParrotRV64(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV64 linker_output_format = "elf64-littleriscv" nop = "nop" - io_regions = {0x50000000: 0x10000000} # origin, length + io_regions = {0x50000000: 0x10000000} # Origin, Length. + # Memory Mapping. @property def mem_map(self): return { @@ -64,6 +74,7 @@ class BlackParrotRV64(CPU): "main_ram" : 0x80000000, } + # GCC Flags. @property def gcc_flags(self): flags = "-mno-save-restore " @@ -80,16 +91,16 @@ class BlackParrotRV64(CPU): self.memory_buses = [] self.cpu_params = dict( - # Clock / Reset + # Clk / Rst. i_clk_i = ClockSignal(), i_reset_i = ResetSignal() | self.reset, - # Wishbone (I/D) + # Wishbone (I/D). i_wbm_dat_i = idbus.dat_r, o_wbm_dat_o = idbus.dat_w, i_wbm_ack_i = idbus.ack, i_wbm_err_i = idbus.err, - #i_wbm_rty_i = 0, + i_wbm_rty_i = Open(), o_wbm_adr_o = idbus.adr, o_wbm_stb_o = idbus.stb, o_wbm_cyc_o = idbus.cyc, @@ -99,7 +110,7 @@ class BlackParrotRV64(CPU): o_wbm_bte_o = idbus.bte, ) - # Add verilog sources + # Add Verilog sources try: os.environ["BP"] os.environ["LITEX"] diff --git a/litex/soc/cores/cpu/cv32e40p/core.py b/litex/soc/cores/cpu/cv32e40p/core.py index 2073abd93..eb24f97e2 100644 --- a/litex/soc/cores/cpu/cv32e40p/core.py +++ b/litex/soc/cores/cpu/cv32e40p/core.py @@ -15,9 +15,12 @@ from litex.soc.interconnect import wishbone, stream from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = ["standard", "full"] +# GCC Flags ---------------------------------------------------------------------------------------- + GCC_FLAGS = { # /-------- Base ISA # |/------- Hardware Multiply + Divide @@ -30,6 +33,8 @@ GCC_FLAGS = { "full": "-march=rv32imfc -mabi=ilp32 ", } +# OBI / APB / Trace Layouts ------------------------------------------------------------------------ + obi_layout = [ ("req", 1), ("gnt", 1), @@ -64,6 +69,8 @@ trace_layout = [ ("compressed", 1), ] +# Helpers ------------------------------------------------------------------------------------------ + def add_manifest_sources(platform, manifest): basedir = get_data_mod("cpu", "cv32e40p").data_location with open(os.path.join(basedir, manifest), 'r') as f: @@ -75,6 +82,7 @@ def add_manifest_sources(platform, manifest): else: platform.add_source(os.path.join(basedir, 'rtl', res.group(1))) +# OBI <> Wishbone ---------------------------------------------------------------------------------- class OBI2Wishbone(Module): def __init__(self, obi, wb): @@ -148,6 +156,8 @@ class Wishbone2OBI(Module): wb.dat_r.eq(obi.rdata), ] +# Wishbone <> APB ---------------------------------------------------------------------------------- + class Wishbone2APB(Module): def __init__(self, wb, apb): self.submodules.fsm = fsm = FSM(reset_state="IDLE") @@ -170,6 +180,8 @@ class Wishbone2APB(Module): wb.dat_r.eq(apb.prdata), ] +# Trace Collector ---------------------------------------------------------------------------------- + class TraceCollector(Module, AutoCSR): def __init__(self, trace_depth=16384): self.bus = bus = wishbone.Interface() @@ -214,6 +226,8 @@ class TraceCollector(Module, AutoCSR): self._pointer.status.eq(pointer), ] +# Trace Debugger ----------------------------------------------------------------------------------- + class TraceDebugger(Module): def __init__(self): self.bus = wishbone.Interface() @@ -225,11 +239,12 @@ class TraceDebugger(Module): self.submodules.bus_conv = Wishbone2APB(self.bus, apb) self.trace_params = dict( - # clk / rst + # Clk / Rst. i_clk_i = ClockSignal(), i_rst_ni = ~ResetSignal(), i_test_mode_i = 0, - # cpu interface + + # CPU Interface. i_ivalid_i = trace_if.ivalid, i_iexception_i = trace_if.iexception, i_interrupt_i = trace_if.interrupt, @@ -239,7 +254,8 @@ class TraceDebugger(Module): i_iaddr_i = trace_if.iaddr, i_instr_i = trace_if.instr, i_compressed_i = trace_if.compressed, - # apb interface + + # APB Interface. i_paddr_i = apb.paddr, i_pwdata_i = apb.pwdata, i_pwrite_i = apb.pwrite, @@ -248,7 +264,8 @@ class TraceDebugger(Module): o_prdata_o = apb.prdata, o_pready_o = apb.pready, o_pslverr_o = apb.pslverr, - # data output + + # Data Output. o_packet_word_o = source.data, o_packet_word_valid_o = source.valid, i_grant_i = source.ready, @@ -259,6 +276,8 @@ class TraceDebugger(Module): def add_sources(platform): add_manifest_sources(platform, "cv32e40p_trace_manifest.flist") +# Debug Module ------------------------------------------------------------------------------------- + class DebugModule(Module): jtag_layout = [ ("tck", 1), @@ -289,18 +308,21 @@ class DebugModule(Module): self.specials += Tristate(pads.tdo, tdo_o, tdo_oe, tdo_i) self.dm_params = dict( + # Clk / Rst. i_clk = ClockSignal(), i_rst_n = ~ResetSignal(), o_ndmreset = self.ndmreset, o_debug_req = self.debug_req, - # slave bus + + # Slave Bus. i_dm_req = dmbus.req, i_dm_we = dmbus.we, i_dm_addr = dmbus.addr, i_dm_be = dmbus.be, i_dm_wdata = dmbus.wdata, o_dm_rdata = dmbus.rdata, - # master bus + + # Master Bus. o_sb_req = sbbus.req, o_sb_addr = sbbus.addr, o_sb_we = sbbus.we, @@ -309,7 +331,8 @@ class DebugModule(Module): i_sb_gnt = sbbus.gnt, i_sb_rvalid = sbbus.rvalid, i_sb_rdata = sbbus.rdata, - # jtag + + # JTAG. i_tck = pads.tck, i_tms = pads.tms, i_trst_n = pads.trst, @@ -329,6 +352,7 @@ class DebugModule(Module): def add_sources(platform): add_manifest_sources(platform, "cv32e40p_dm_manifest.flist") +# CV32E40P ----------------------------------------------------------------------------------------- class CV32E40P(CPU): name = "cv32e40p" @@ -339,15 +363,15 @@ class CV32E40P(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV32 linker_output_format = "elf32-littleriscv" nop = "nop" - io_regions = {0x80000000: 0x80000000} # origin, length + io_regions = {0x80000000: 0x80000000} # Origin, Length. has_fpu = ["full"] + # GCC Flags. @property def gcc_flags(self): flags = GCC_FLAGS[self.variant] flags += "-D__cv32e40p__ " - return flags def __init__(self, platform, variant="standard"): @@ -363,6 +387,7 @@ class CV32E40P(CPU): ibus = Record(obi_layout) dbus = Record(obi_layout) + # OBI <> Wishbone. self.submodules.ibus_conv = OBI2Wishbone(ibus, self.ibus) self.submodules.dbus_conv = OBI2Wishbone(dbus, self.dbus) @@ -372,20 +397,25 @@ class CV32E40P(CPU): ] self.cpu_params = dict( + # Clk / Rst. i_clk_i = ClockSignal(), i_rst_ni = ~ResetSignal(), + + # Controls. i_clock_en_i = 1, i_test_en_i = 0, i_fregfile_disable_i = 0, i_core_id_i = 0, i_cluster_id_i = 0, - # ibus + + # IBus. o_instr_req_o = ibus.req, i_instr_gnt_i = ibus.gnt, i_instr_rvalid_i = ibus.rvalid, o_instr_addr_o = ibus.addr, i_instr_rdata_i = ibus.rdata, - # dbus + + # DBus. o_data_req_o = dbus.req, i_data_gnt_i = dbus.gnt, i_data_rvalid_i = dbus.rvalid, @@ -394,25 +424,30 @@ class CV32E40P(CPU): o_data_addr_o = dbus.addr, o_data_wdata_o = dbus.wdata, i_data_rdata_i = dbus.rdata, - # apu + + # APU. i_apu_master_gnt_i = 0, i_apu_master_valid_i = 0, - # ir q + + # IRQ. i_irq_sec_i = 0, i_irq_software_i = 0, i_irq_external_i = 0, i_irq_fast_i = self.interrupt, i_irq_nmi_i = 0, i_irq_fastx_i = 0, - # debug + + # Debug. i_debug_req_i = 0, - # cpu control + + # CPU Control. i_fetch_enable_i = 1, ) - # add verilog sources + # Add Verilog sources. add_manifest_sources(platform, 'cv32e40p_manifest.flist') + # Specific FPU variant parameters/files. if variant in self.has_fpu: self.cpu_params.update(p_FPU=1) add_manifest_sources(platform, 'cv32e40p_fpu_manifest.flist') diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index 13314501d..7ed738e39 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -13,9 +13,14 @@ from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +class Open(Signal): pass + +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = ["standard"] +# GCC Flags ---------------------------------------------------------------------------------------- + GCC_FLAGS = { # /-------- Base ISA # |/------- Hardware Multiply + Divide @@ -27,6 +32,8 @@ GCC_FLAGS = { "standard": "-march=rv32imc -mabi=ilp32 ", } +# OBI <> Wishbone ---------------------------------------------------------------------------------- + obi_layout = [ ("req", 1), ("gnt", 1), @@ -88,6 +95,7 @@ class OBI2Wishbone(Module): ) ) +# Ibex --------------------------------------------------------------------------------------------- class Ibex(CPU): name = "ibex" @@ -98,8 +106,9 @@ class Ibex(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV32 linker_output_format = "elf32-littleriscv" nop = "nop" - io_regions = {0x80000000: 0x80000000} # origin, length + io_regions = {0x80000000: 0x80000000} # Origin, Length. + # GCC Flags. @property def gcc_flags(self): flags = GCC_FLAGS[self.variant] @@ -118,6 +127,7 @@ class Ibex(CPU): ibus = Record(obi_layout) dbus = Record(obi_layout) + # OBI <> Wishbone. self.submodules.ibus_conv = OBI2Wishbone(ibus, self.ibus) self.submodules.dbus_conv = OBI2Wishbone(dbus, self.dbus) @@ -126,18 +136,17 @@ class Ibex(CPU): ibus.be.eq(1111), ] - class Open(Signal): pass self.cpu_params = dict( - # Configuration + # Configuration. p_RegFile = 1, # RegFileFPGA i_test_en_i = 0, i_hart_id_i = 0, - # Clk/Rst + # Clk/Rst. i_clk_i = ClockSignal(), i_rst_ni = ~ResetSignal(), - # Instruction bus + # Instruction bus. o_instr_req_o = ibus.req, i_instr_gnt_i = ibus.gnt, i_instr_rvalid_i = ibus.rvalid, @@ -145,7 +154,7 @@ class Ibex(CPU): i_instr_rdata_i = ibus.rdata, i_instr_err_i = 0, - # Data bus + # Data bus. o_data_req_o = dbus.req, i_data_gnt_i = dbus.gnt, i_data_rvalid_i = dbus.rvalid, @@ -156,24 +165,24 @@ class Ibex(CPU): i_data_rdata_i = dbus.rdata, i_data_err_i = 0, - # Interrupts + # Interrupts. i_irq_software_i = 0, i_irq_timer_i = 0, i_irq_external_i = 0, i_irq_fast_i = 0, i_irq_nm_i = 0, - # Debug + # Debug. i_debug_req_i = 0, - # Control/Status + # Control/Status. i_fetch_enable_i = 1, o_alert_minor_o = Open(), o_alert_major_o = Open(), o_core_sleep_o = Open() ) - # Add verilog sources + # Add Verilog sources self.add_sources(platform) @staticmethod diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 0276067ff..f7ac550b0 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -16,8 +16,11 @@ from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU +# Variants ----------------------------------------------------------------------------------------- + CPU_VARIANTS = ["minimal", "lite", "standard"] +# LM32 --------------------------------------------------------------------------------------------- class LM32(CPU): name = "lm32" @@ -30,6 +33,7 @@ class LM32(CPU): nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length + # GCC Flags. @property def gcc_flags(self): flags = "-mbarrel-shift-enabled " @@ -43,55 +47,52 @@ class LM32(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.ibus = i = wishbone.Interface() - self.dbus = d = wishbone.Interface() + self.ibus = ibus = wishbone.Interface() + self.dbus = dbus = wishbone.Interface() self.interrupt = Signal(32) - self.periph_buses = [i, d] - self.memory_buses = [] + self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # - i_adr_o = Signal(32) - d_adr_o = Signal(32) self.cpu_params = dict( - i_clk_i=ClockSignal(), - i_rst_i=ResetSignal() | self.reset, + # Clk / Rst. + i_clk_i = ClockSignal(), + i_rst_i = ResetSignal() | self.reset, + # IRQ. i_interrupt=self.interrupt, - o_I_ADR_O = i_adr_o, - o_I_DAT_O = i.dat_w, - o_I_SEL_O = i.sel, - o_I_CYC_O = i.cyc, - o_I_STB_O = i.stb, - o_I_WE_O = i.we, - o_I_CTI_O = i.cti, - o_I_BTE_O = i.bte, - i_I_DAT_I = i.dat_r, - i_I_ACK_I = i.ack, - i_I_ERR_I = i.err, + # IBus. + o_I_ADR_O = Cat(Signal(2), ibus.adr), + o_I_DAT_O = ibus.dat_w, + o_I_SEL_O = ibus.sel, + o_I_CYC_O = ibus.cyc, + o_I_STB_O = ibus.stb, + o_I_WE_O = ibus.we, + o_I_CTI_O = ibus.cti, + o_I_BTE_O = ibus.bte, + i_I_DAT_I = ibus.dat_r, + i_I_ACK_I = ibus.ack, + i_I_ERR_I = ibus.err, i_I_RTY_I = 0, - o_D_ADR_O = d_adr_o, - o_D_DAT_O = d.dat_w, - o_D_SEL_O = d.sel, - o_D_CYC_O = d.cyc, - o_D_STB_O = d.stb, - o_D_WE_O = d.we, - o_D_CTI_O = d.cti, - o_D_BTE_O = d.bte, - i_D_DAT_I = d.dat_r, - i_D_ACK_I = d.ack, - i_D_ERR_I = d.err, + # DBus. + o_D_ADR_O = Cat(Signal(2), dbus.adr), + o_D_DAT_O = dbus.dat_w, + o_D_SEL_O = dbus.sel, + o_D_CYC_O = dbus.cyc, + o_D_STB_O = dbus.stb, + o_D_WE_O = dbus.we, + o_D_CTI_O = dbus.cti, + o_D_BTE_O = dbus.bte, + i_D_DAT_I = dbus.dat_r, + i_D_ACK_I = dbus.ack, + i_D_ERR_I = dbus.err, i_D_RTY_I = 0, ) - self.comb += [ - self.ibus.adr.eq(i_adr_o[2:]), - self.dbus.adr.eq(d_adr_o[2:]) - ] - - # add verilog sources + # Add Verilog sources. self.add_sources(platform, variant) def set_reset_address(self, reset_address): diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 4acef6289..953db7569 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -16,8 +16,14 @@ from litex.soc.interconnect.csr import * from litex.gen.common import reverse_bytes from litex.soc.cores.cpu import CPU +class Open(Signal): pass + +# Variants ----------------------------------------------------------------------------------------- + CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq"] +# Microwatt ---------------------------------------------------------------------------------------- + class Microwatt(CPU): name = "microwatt" human_name = "Microwatt" @@ -27,8 +33,9 @@ class Microwatt(CPU): gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu") linker_output_format = "elf64-powerpcle" nop = "nop" - io_regions = {0xc0000000: 0x10000000} # origin, length + io_regions = {0xc0000000: 0x10000000} # Origin, Length. + # Memory Mapping. @property def mem_map(self): return { @@ -37,6 +44,7 @@ class Microwatt(CPU): "xicsics": 0xc3ff1000 } + # GCC Flags. @property def gcc_flags(self): flags = "-m64 " @@ -57,58 +65,58 @@ class Microwatt(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=29) - self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=29) - self.periph_buses = [wb_insn, wb_data] - self.memory_buses = [] + self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29) + self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29) + self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). if "irq" in variant: - self.interrupt = Signal(16) + self.interrupt = Signal(16) self.core_ext_irq = Signal() # # # self.cpu_params = dict( - # Clock / Reset - i_clk = ClockSignal(), - i_rst = ResetSignal() | self.reset, + # Clk / Rst. + i_clk = ClockSignal(), + i_rst = ResetSignal() | self.reset, - # Wishbone instruction bus - i_wishbone_insn_dat_r = wb_insn.dat_r, - i_wishbone_insn_ack = wb_insn.ack, - i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support + # IBus. + i_wishbone_insn_dat_r = ibus.dat_r, + i_wishbone_insn_ack = ibus.ack, + i_wishbone_insn_stall = ibus.cyc & ~ibus.ack, # No burst support - o_wishbone_insn_adr = Cat(Signal(3), wb_insn.adr), - o_wishbone_insn_dat_w = wb_insn.dat_w, - o_wishbone_insn_cyc = wb_insn.cyc, - o_wishbone_insn_stb = wb_insn.stb, - o_wishbone_insn_sel = wb_insn.sel, - o_wishbone_insn_we = wb_insn.we, + o_wishbone_insn_adr = Cat(Signal(3), ibus.adr), + o_wishbone_insn_dat_w = ibus.dat_w, + o_wishbone_insn_cyc = ibus.cyc, + o_wishbone_insn_stb = ibus.stb, + o_wishbone_insn_sel = ibus.sel, + o_wishbone_insn_we = ibus.we, - # Wishbone data bus - i_wishbone_data_dat_r = wb_data.dat_r, - i_wishbone_data_ack = wb_data.ack, - i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support + # DBus. + i_wishbone_data_dat_r = dbus.dat_r, + i_wishbone_data_ack = dbus.ack, + i_wishbone_data_stall = dbus.cyc & ~dbus.ack, # No burst support - o_wishbone_data_adr = Cat(Signal(3), wb_data.adr), - o_wishbone_data_dat_w = wb_data.dat_w, - o_wishbone_data_cyc = wb_data.cyc, - o_wishbone_data_stb = wb_data.stb, - o_wishbone_data_sel = wb_data.sel, - o_wishbone_data_we = wb_data.we, + o_wishbone_data_adr = Cat(Signal(3), dbus.adr), + o_wishbone_data_dat_w = dbus.dat_w, + o_wishbone_data_cyc = dbus.cyc, + o_wishbone_data_stb = dbus.stb, + o_wishbone_data_sel = dbus.sel, + o_wishbone_data_we = dbus.we, - # Debug bus - i_dmi_addr = 0, - i_dmi_din = 0, - #o_dmi_dout =, - i_dmi_req = 0, - i_dmi_wr = 0, - #o_dmi_ack =, + # Debug. + i_dmi_addr = 0, + i_dmi_din = 0, + o_dmi_dout = Open(), + i_dmi_req = 0, + i_dmi_wr = 0, + o_dmi_ack = Open(), - # Interrupt controller - i_core_ext_irq = self.core_ext_irq, + # IRQ. + i_core_ext_irq = self.core_ext_irq, ) - # add vhdl sources + # Add VHDL sources. self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) def set_reset_address(self, reset_address): @@ -132,23 +140,23 @@ class Microwatt(CPU): @staticmethod def add_sources(platform, use_ghdl_yosys_plugin=False): sources = [ - # Common / Types / Helpers + # Common / Types / Helpers. "decode_types.vhdl", "wishbone_types.vhdl", "utils.vhdl", "common.vhdl", "helpers.vhdl", - # Fetch + # Fetch. "fetch1.vhdl", - # Instruction/Data Cache + # Instruction/Data Cache. "cache_ram.vhdl", "plru.vhdl", "dcache.vhdl", "icache.vhdl", - # Decode + # Decode. "insn_helpers.vhdl", "decode1.vhdl", "gpr_hazard.vhdl", @@ -156,37 +164,38 @@ class Microwatt(CPU): "control.vhdl", "decode2.vhdl", - # Register/CR File + # Register/CR File. "register_file.vhdl", "crhelpers.vhdl", "cr_file.vhdl", - # Execute + # Execute. "ppc_fx_insns.vhdl", "logical.vhdl", "rotator.vhdl", "countzero.vhdl", "execute1.vhdl", - # Load/Store + # Load/Store. "loadstore1.vhdl", - # Multiply/Divide + # Multiply/Divide. "multiply.vhdl", "divider.vhdl", - # Writeback + # Writeback. "writeback.vhdl", - # MMU + # MMU. "mmu.vhdl", - # Core + # Core. "core_debug.vhdl", "core.vhdl", ] sdir = get_data_mod("cpu", "microwatt").data_location cdir = os.path.dirname(__file__) + # Convert VHDL to Verilog through GHDL/Yosys. if use_ghdl_yosys_plugin: from litex.build import tools import subprocess @@ -202,6 +211,7 @@ class Microwatt(CPU): if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]): raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install") platform.add_source(os.path.join(cdir, "microwatt.v")) + # Direct use of VHDL sources. else: platform.add_sources(sdir, *sources) platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl")) @@ -209,24 +219,25 @@ class Microwatt(CPU): def do_finalize(self): self.specials += Instance("microwatt_wrapper", **self.cpu_params) +# XICS Slave --------------------------------------------------------------------------------------- class XICSSlave(Module, AutoCSR): def __init__(self, platform, core_irq_out=Signal(), int_level_in=Signal(16), variant="standard"): self.variant = variant - self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12) - self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12) + self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12) + self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12) - # XICS signals + # XICS signals. self.ics_icp_xfer_src = Signal(4) self.ics_icp_xfer_pri = Signal(8) self.icp_params = dict( - # Clock / Reset + # Clk / Rst. i_clk = ClockSignal(), i_rst = ResetSignal(), - # Wishbone bus + # Wishbone Bus. o_wishbone_dat_r = icp_bus.dat_r, o_wishbone_ack = icp_bus.ack, @@ -244,11 +255,11 @@ class XICSSlave(Module, AutoCSR): ) self.ics_params = dict( - # Clock / Reset + # Clk / Rst. i_clk = ClockSignal(), i_rst = ResetSignal(), - # Wishbone bus + # Wishbone Bus. o_wishbone_dat_r = ics_bus.dat_r, o_wishbone_ack = ics_bus.ack, @@ -265,7 +276,7 @@ class XICSSlave(Module, AutoCSR): o_icp_out_pri = self.ics_icp_xfer_pri, ) - # add vhdl sources + # Add VHDL sources. self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) @staticmethod diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index d02df7600..0a384736d 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -14,8 +14,11 @@ from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +# Variants ----------------------------------------------------------------------------------------- + CPU_VARIANTS = ["standard"] +# Minerva ------------------------------------------------------------------------------------------ class Minerva(CPU): name = "minerva" @@ -26,8 +29,9 @@ class Minerva(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV32 linker_output_format = "elf32-littleriscv" nop = "nop" - io_regions = {0x80000000: 0x80000000} # origin, length + io_regions = {0x80000000: 0x80000000} # Origin, Length. + # GCC Flags. @property def gcc_flags(self): flags = "-march=rv32im " @@ -40,53 +44,48 @@ class Minerva(CPU): self.variant = variant self.reset = Signal() self.interrupt = Signal(32) - self.ibus = wishbone.Interface() - self.dbus = wishbone.Interface() - self.periph_buses = [self.ibus, self.dbus] - self.memory_buses = [] - - # TODO: create variants - self.with_icache = False - self.with_dcache = False - self.with_muldiv = True + self.ibus = ibus = wishbone.Interface() + self.dbus = dbus = wishbone.Interface() + self.periph_buses = [self.ibus, self.dbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # self.cpu_params = dict( - # clock / reset - i_clk=ClockSignal(), - i_rst=ResetSignal() | self.reset, + # Clk / Rst. + i_clk = ClockSignal(), + i_rst = ResetSignal() | self.reset, - # interrupts + # IRQ. i_timer_interrupt = 0, i_software_interrupt = 0, i_external_interrupt = self.interrupt, - # ibus - o_ibus__stb = self.ibus.stb, - o_ibus__cyc = self.ibus.cyc, - o_ibus__cti = self.ibus.cti, - o_ibus__bte = self.ibus.bte, - o_ibus__we = self.ibus.we, - o_ibus__adr = self.ibus.adr, - o_ibus__dat_w = self.ibus.dat_w, - o_ibus__sel = self.ibus.sel, - i_ibus__ack = self.ibus.ack, - i_ibus__err = self.ibus.err, - i_ibus__dat_r = self.ibus.dat_r, + # Ibus. + o_ibus__stb = ibus.stb, + o_ibus__cyc = ibus.cyc, + o_ibus__cti = ibus.cti, + o_ibus__bte = ibus.bte, + o_ibus__we = ibus.we, + o_ibus__adr = ibus.adr, + o_ibus__dat_w = ibus.dat_w, + o_ibus__sel = ibus.sel, + i_ibus__ack = ibus.ack, + i_ibus__err = ibus.err, + i_ibus__dat_r = ibus.dat_r, - # dbus - o_dbus__stb = self.dbus.stb, - o_dbus__cyc = self.dbus.cyc, - o_dbus__cti = self.dbus.cti, - o_dbus__bte = self.dbus.bte, - o_dbus__we = self.dbus.we, - o_dbus__adr = self.dbus.adr, - o_dbus__dat_w = self.dbus.dat_w, - o_dbus__sel = self.dbus.sel, - i_dbus__ack = self.dbus.ack, - i_dbus__err = self.dbus.err, - i_dbus__dat_r = self.dbus.dat_r, + # Dbus. + o_dbus__stb = dbus.stb, + o_dbus__cyc = dbus.cyc, + o_dbus__cti = dbus.cti, + o_dbus__bte = dbus.bte, + o_dbus__we = dbus.we, + o_dbus__adr = dbus.adr, + o_dbus__dat_w = dbus.dat_w, + o_dbus__sel = dbus.sel, + i_dbus__ack = dbus.ack, + i_dbus__err = dbus.err, + i_dbus__dat_r = dbus.dat_r, ) def set_reset_address(self, reset_address): @@ -115,9 +114,9 @@ class Minerva(CPU): verilog_filename = os.path.join(self.platform.output_dir, "gateware", "minerva.v") self.elaborate( reset_address = self.reset_address, - with_icache = self.with_icache, - with_dcache = self.with_dcache, - with_muldiv = self.with_muldiv, + with_icache = True, + with_dcache = True, + with_muldiv = True, verilog_filename = verilog_filename) self.platform.add_source(verilog_filename) self.specials += Instance("minerva_cpu", **self.cpu_params) diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index f6714f534..50c675840 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -15,9 +15,11 @@ from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU -CPU_VARIANTS = ["standard", "standard+fpu", "linux", "linux+fpu", - "linux+smp", "linux+smp+fpu"] +# Variants ----------------------------------------------------------------------------------------- +CPU_VARIANTS = ["standard", "standard+fpu", "linux", "linux+fpu", "linux+smp", "linux+smp+fpu"] + +# Mor1kx ------------------------------------------------------------------------------------------- class MOR1KX(CPU): name = "mor1kx" @@ -29,8 +31,9 @@ class MOR1KX(CPU): clang_triple = "or1k-linux" linker_output_format = "elf32-or1k" nop = "l.nop" - io_regions = {0x80000000: 0x80000000} # origin, length + io_regions = {0x80000000: 0x80000000} # Origin, Length. + # Memory Mapping for Linux variant. @property def mem_map_linux(self): # Mainline Linux OpenRISC arch code requires Linux kernel to be loaded at the physical @@ -43,10 +46,12 @@ class MOR1KX(CPU): "csr" : 0xe0000000, } + # GCC Triple. @property def gcc_triple(self): return "or1k-elf" + # GCC Flags. @property def gcc_flags(self): flags = "-mhard-mul " @@ -60,6 +65,7 @@ class MOR1KX(CPU): return flags + # Clang Flags. @property def clang_flags(self): flags = "-mhard-mul " @@ -69,6 +75,7 @@ class MOR1KX(CPU): flags += "-D__mor1kx__ " return flags + # Reserved Interrupts. @property def reserved_interrupts(self): return {"nmi": 0} @@ -78,17 +85,14 @@ class MOR1KX(CPU): self.variant = variant self.reset = Signal() self.interrupt = Signal(32) - self.ibus = i = wishbone.Interface() - self.dbus = d = wishbone.Interface() - self.periph_buses = [i, d] - self.memory_buses = [] - - - if "linux" in variant: - self.mem_map = self.mem_map_linux + self.ibus = ibus = wishbone.Interface() + self.dbus = dbus = wishbone.Interface() + self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # + # CPU parameters. cpu_args = dict( p_FEATURE_INSTRUCTIONCACHE = "ENABLED", p_OPTION_ICACHE_BLOCK_WIDTH = 4, @@ -100,30 +104,29 @@ class MOR1KX(CPU): p_OPTION_DCACHE_SET_WIDTH = 8, p_OPTION_DCACHE_WAYS = 1, p_OPTION_DCACHE_LIMIT_WIDTH = 31, - p_FEATURE_TIMER = "NONE", - p_OPTION_PIC_TRIGGER = "LEVEL", - p_FEATURE_SYSCALL = "NONE", - p_FEATURE_TRAP = "NONE", - p_FEATURE_RANGE = "NONE", - p_FEATURE_OVERFLOW = "NONE", - p_FEATURE_ADDC = "ENABLED", - p_FEATURE_CMOV = "ENABLED", - p_FEATURE_FFL1 = "ENABLED", - p_OPTION_CPU0 = "CAPPUCCINO", - p_IBUS_WB_TYPE = "B3_REGISTERED_FEEDBACK", - p_DBUS_WB_TYPE = "B3_REGISTERED_FEEDBACK", + p_FEATURE_TIMER = "NONE", + p_OPTION_PIC_TRIGGER = "LEVEL", + p_FEATURE_SYSCALL = "NONE", + p_FEATURE_TRAP = "NONE", + p_FEATURE_RANGE = "NONE", + p_FEATURE_OVERFLOW = "NONE", + p_FEATURE_ADDC = "ENABLED", + p_FEATURE_CMOV = "ENABLED", + p_FEATURE_FFL1 = "ENABLED", + p_OPTION_CPU0 = "CAPPUCCINO", + p_IBUS_WB_TYPE = "B3_REGISTERED_FEEDBACK", + p_DBUS_WB_TYPE = "B3_REGISTERED_FEEDBACK", ) + # SMP parameters. if "smp" in variant: - cpu_args.update( - p_OPTION_RF_NUM_SHADOW_GPR = 1, - ) + cpu_args.update(p_OPTION_RF_NUM_SHADOW_GPR=1) + # FPU parameters. if "fpu" in variant: - cpu_args.update( - p_FEATURE_FPU = "ENABLED", - ) + cpu_args.update(p_FEATURE_FPU = "ENABLED") + # Linux parameters if "linux" in variant: cpu_args.update( # Linux needs the memory management units. @@ -135,6 +138,8 @@ class MOR1KX(CPU): p_FEATURE_ROR = "ENABLED", p_FEATURE_EXT = "ENABLED", ) + # Linux variant requires specific Memory Mapping. + self.mem_map = self.mem_map_linux # FIXME: Check if these are needed? use_defaults = ( "p_FEATURE_SYSCALL", @@ -145,49 +150,46 @@ class MOR1KX(CPU): for to_remove in use_defaults: del cpu_args[to_remove] - i_adr_o = Signal(32) - d_adr_o = Signal(32) self.cpu_params = dict( **cpu_args, - i_clk=ClockSignal(), - i_rst=ResetSignal() | self.reset, + # Clk / Rst. + i_clk = ClockSignal(), + i_rst = ResetSignal() | self.reset, + # IRQ. i_irq_i=self.interrupt, - o_iwbm_adr_o = i_adr_o, - o_iwbm_dat_o = i.dat_w, - o_iwbm_sel_o = i.sel, - o_iwbm_cyc_o = i.cyc, - o_iwbm_stb_o = i.stb, - o_iwbm_we_o = i.we, - o_iwbm_cti_o = i.cti, - o_iwbm_bte_o = i.bte, - i_iwbm_dat_i = i.dat_r, - i_iwbm_ack_i = i.ack, - i_iwbm_err_i = i.err, + # IBus. + o_iwbm_adr_o = Cat(Signal(2), ibus.adr), + o_iwbm_dat_o = ibus.dat_w, + o_iwbm_sel_o = ibus.sel, + o_iwbm_cyc_o = ibus.cyc, + o_iwbm_stb_o = ibus.stb, + o_iwbm_we_o = ibus.we, + o_iwbm_cti_o = ibus.cti, + o_iwbm_bte_o = ibus.bte, + i_iwbm_dat_i = ibus.dat_r, + i_iwbm_ack_i = ibus.ack, + i_iwbm_err_i = ibus.err, i_iwbm_rty_i = 0, - o_dwbm_adr_o = d_adr_o, - o_dwbm_dat_o = d.dat_w, - o_dwbm_sel_o = d.sel, - o_dwbm_cyc_o = d.cyc, - o_dwbm_stb_o = d.stb, - o_dwbm_we_o = d.we, - o_dwbm_cti_o = d.cti, - o_dwbm_bte_o = d.bte, - i_dwbm_dat_i = d.dat_r, - i_dwbm_ack_i = d.ack, - i_dwbm_err_i = d.err, + # DBus. + o_dwbm_adr_o = Cat(Signal(2), dbus.adr), + o_dwbm_dat_o = dbus.dat_w, + o_dwbm_sel_o = dbus.sel, + o_dwbm_cyc_o = dbus.cyc, + o_dwbm_stb_o = dbus.stb, + o_dwbm_we_o = dbus.we, + o_dwbm_cti_o = dbus.cti, + o_dwbm_bte_o = dbus.bte, + i_dwbm_dat_i = dbus.dat_r, + i_dwbm_ack_i = dbus.ack, + i_dwbm_err_i = dbus.err, i_dwbm_rty_i = 0, ) - self.comb += [ - self.ibus.adr.eq(i_adr_o[2:]), - self.dbus.adr.eq(d_adr_o[2:]) - ] - - # add verilog sources + # Add Verilog sources. self.add_sources(platform) def set_reset_address(self, reset_address): diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 8f870dc17..9ad28ef44 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -16,9 +16,12 @@ from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = ["minimal", "standard"] +# GCC Flags ---------------------------------------------------------------------------------------- + GCC_FLAGS = { # /-------- Base ISA # |/------- Hardware Multiply + Divide @@ -31,6 +34,7 @@ GCC_FLAGS = { "standard": "-march=rv32im -mabi=ilp32 ", } +# PicoRV32 ----------------------------------------------------------------------------------------- class PicoRV32(CPU): name = "picorv32" @@ -43,6 +47,7 @@ class PicoRV32(CPU): nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length + # GCC Flags. @property def gcc_flags(self): flags = "-mno-save-restore " @@ -50,6 +55,7 @@ class PicoRV32(CPU): flags += "-D__picorv32__ " return flags + # Reserved Interrupts. @property def reserved_interrupts(self): return { @@ -65,8 +71,8 @@ class PicoRV32(CPU): self.reset = Signal() self.interrupt = Signal(32) self.idbus = idbus = wishbone.Interface() - self.periph_buses = [idbus] - self.memory_buses = [] + self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # @@ -78,15 +84,12 @@ class PicoRV32(CPU): mem_wstrb = Signal(4) mem_rdata = Signal(32) - # PicoRV32 parameters. To create a new variant, modify this dictionary - # and change the desired parameters. + # PicoRV32 parameters, change the desired parameters to create a create a new variant. self.cpu_params = dict( p_ENABLE_COUNTERS = 1, p_ENABLE_COUNTERS64 = 1, - # Changing REGS has no effect as on FPGAs, the registers are - # implemented using a register file stored in DPRAM. - p_ENABLE_REGS_16_31 = 1, - p_ENABLE_REGS_DUALPORT = 1, + p_ENABLE_REGS_16_31 = 1, # Changing REGS has no effect as on FPGAs, the regs are + p_ENABLE_REGS_DUALPORT = 1, # implemented using a register file stored in DPRAM. p_LATCHED_MEM_RDATA = 0, p_TWO_STAGE_SHIFT = 1, p_TWO_CYCLE_COMPARE = 0, @@ -106,6 +109,7 @@ class PicoRV32(CPU): p_STACKADDR = 0xffffffff, ) + # Enforce default parameters for Minimal variant. if variant == "minimal": self.cpu_params.update( p_ENABLE_COUNTERS = 0, @@ -118,14 +122,14 @@ class PicoRV32(CPU): ) self.cpu_params.update( - # clock / reset - i_clk =ClockSignal(), - i_resetn =~(ResetSignal() | self.reset), + # Clk / Rst. + i_clk = ClockSignal(), + i_resetn = ~(ResetSignal() | self.reset), - # trap - o_trap=self.trap, + # Trap. + o_trap = self.trap, - # memory interface + # Memory Interface. o_mem_valid = mem_valid, o_mem_instr = mem_instr, i_mem_ready = mem_ready, @@ -135,14 +139,14 @@ class PicoRV32(CPU): o_mem_wstrb = mem_wstrb, i_mem_rdata = mem_rdata, - # look ahead interface (not used) + # Look Ahead Interface (not used). o_mem_la_read = Signal(), o_mem_la_write = Signal(), o_mem_la_addr = Signal(32), o_mem_la_wdata = Signal(32), o_mem_la_wstrb = Signal(4), - # co-processor interface (not used) + # Co-Processor interface (not used). o_pcpi_valid = Signal(), o_pcpi_insn = Signal(32), o_pcpi_rs1 = Signal(32), @@ -152,11 +156,11 @@ class PicoRV32(CPU): i_pcpi_wait = 0, i_pcpi_ready = 0, - # irq interface + # IRQ interface. i_irq = self.interrupt, o_eoi = Signal(32)) # not used - # adapt memory interface to wishbone + # Adapt Memory Interface to Wishbone. self.comb += [ idbus.adr.eq(mem_addr[2:]), idbus.dat_w.eq(mem_wdata), @@ -170,7 +174,7 @@ class PicoRV32(CPU): mem_rdata.eq(idbus.dat_r), ] - # add verilog sources + # Add Verilog sources self.add_sources(platform) def set_reset_address(self, reset_address): diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index c1962f16d..80ec86ef8 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -38,6 +38,9 @@ from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64 +class Open(Signal): pass + +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = { "standard": "freechips.rocketchip.system.LitexConfig", @@ -47,6 +50,8 @@ CPU_VARIANTS = { "full": "freechips.rocketchip.system.LitexFullConfig", } +# GCC Flags----------------------------------------------------------------------------------------- + GCC_FLAGS = { "standard": "-march=rv64imac -mabi=lp64 ", "linux": "-march=rv64imac -mabi=lp64 ", @@ -55,8 +60,10 @@ GCC_FLAGS = { "full": "-march=rv64imafdc -mabi=lp64 ", } +# AXI Data-Widths ---------------------------------------------------------------------------------- + AXI_DATA_WIDTHS = { - # variant : (mem, mmio) + # Variant : (mem, mmio) "standard": ( 64, 64), "linux": ( 64, 64), "linuxd": (128, 64), @@ -64,6 +71,8 @@ AXI_DATA_WIDTHS = { "full": ( 64, 64), } +# Rocket RV64 -------------------------------------------------------------------------------------- + class RocketRV64(CPU): name = "rocket" human_name = "RocketRV64[imac]" @@ -73,8 +82,9 @@ class RocketRV64(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV64 linker_output_format = "elf64-littleriscv" nop = "nop" - io_regions = {0x10000000: 0x70000000} # origin, length + io_regions = {0x10000000: 0x70000000} # Origin, Length. + # Memory Mapping. @property def mem_map(self): # Rocket reserves the first 256Mbytes for internal use, so we must change default mem_map. @@ -86,6 +96,7 @@ class RocketRV64(CPU): "main_ram" : 0x80000000, } + # GCC Flags. @property def gcc_flags(self): flags = "-mno-save-restore " @@ -109,40 +120,40 @@ class RocketRV64(CPU): self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8)) self.l2fb_wb = l2fb_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8)) - self.memory_buses = [mem_axi] - self.periph_buses = [mmio_wb] - self.dma_bus = l2fb_wb + self.memory_buses = [mem_axi] # Peripheral buses (Connected to main SoC's bus). + self.periph_buses = [mmio_wb] # Memory buses (Connected directly to LiteDRAM). + self.dma_bus = l2fb_wb # DMA bus (Arbitrated and connected to SoC's bus). # # # self.cpu_params = dict( - # clock, reset - i_clock=ClockSignal(), - i_reset=ResetSignal() | self.reset, + # Clk / Rst. + i_clock = ClockSignal(), + i_reset = ResetSignal() | self.reset, - # debug (ignored) - #i_resetctrl_hartIsInReset_0 = 0, - i_debug_clock = 0, - i_debug_reset = ResetSignal() | self.reset, - #o_debug_clockeddmi_dmi_req_ready = , - i_debug_clockeddmi_dmi_req_valid = 0, - i_debug_clockeddmi_dmi_req_bits_addr = 0, - i_debug_clockeddmi_dmi_req_bits_data = 0, - i_debug_clockeddmi_dmi_req_bits_op = 0, - i_debug_clockeddmi_dmi_resp_ready = 0, - #o_debug_clockeddmi_dmi_resp_valid = , - #o_debug_clockeddmi_dmi_resp_bits_data = , - #o_debug_clockeddmi_dmi_resp_bits_resp = , - i_debug_clockeddmi_dmiClock = 0, - i_debug_clockeddmi_dmiReset = ResetSignal() | self.reset, - #o_debug_ndreset = , - #o_debug_dmactive = , - i_debug_dmactiveAck = 0, + # Debug (ignored). + i_resetctrl_hartIsInReset_0 = Open(), + i_debug_clock = 0, + i_debug_reset = ResetSignal() | self.reset, + o_debug_clockeddmi_dmi_req_ready = Open(), + i_debug_clockeddmi_dmi_req_valid = 0, + i_debug_clockeddmi_dmi_req_bits_addr = 0, + i_debug_clockeddmi_dmi_req_bits_data = 0, + i_debug_clockeddmi_dmi_req_bits_op = 0, + i_debug_clockeddmi_dmi_resp_ready = 0, + o_debug_clockeddmi_dmi_resp_valid = Open(), + o_debug_clockeddmi_dmi_resp_bits_data = Open(), + o_debug_clockeddmi_dmi_resp_bits_resp = Open(), + i_debug_clockeddmi_dmiClock = 0, + i_debug_clockeddmi_dmiReset = ResetSignal() | self.reset, + o_debug_ndreset = Open(), + o_debug_dmactive = Open(), + i_debug_dmactiveAck = 0, - # irq - i_interrupts=self.interrupt, + # IRQ. + i_interrupts = self.interrupt, - # axi memory (L1-cached) + # AXI Memory (L1-cached). i_mem_axi4_0_aw_ready = mem_axi.aw.ready, o_mem_axi4_0_aw_valid = mem_axi.aw.valid, o_mem_axi4_0_aw_bits_id = mem_axi.aw.id, @@ -185,7 +196,7 @@ class RocketRV64(CPU): i_mem_axi4_0_r_bits_resp = mem_axi.r.resp, i_mem_axi4_0_r_bits_last = mem_axi.r.last, - # axi mmio (not cached) + # AXI MMIO (not cached). i_mmio_axi4_0_aw_ready = mmio_axi.aw.ready, o_mmio_axi4_0_aw_valid = mmio_axi.aw.valid, o_mmio_axi4_0_aw_bits_id = mmio_axi.aw.id, @@ -228,7 +239,7 @@ class RocketRV64(CPU): i_mmio_axi4_0_r_bits_resp = mmio_axi.r.resp, i_mmio_axi4_0_r_bits_last = mmio_axi.r.last, - # axi l2fb (slave, for e.g., DMA) + # AXI L2FB (Slave, for e.g., DMA). o_l2_frontend_bus_axi4_0_aw_ready = l2fb_axi.aw.ready, i_l2_frontend_bus_axi4_0_aw_valid = l2fb_axi.aw.valid, i_l2_frontend_bus_axi4_0_aw_bits_id = l2fb_axi.aw.id, @@ -272,17 +283,16 @@ class RocketRV64(CPU): o_l2_frontend_bus_axi4_0_r_bits_last = l2fb_axi.r.last, ) - # adapt axi interfaces to wishbone - # NOTE: AXI2Wishbone FSMs must be reset with the CPU! + # Adapt AXI interfaces to Wishbone. mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)) - self.comb += mmio_a2w.reset.eq(ResetSignal() | self.reset) + self.comb += mmio_a2w.reset.eq(ResetSignal() | self.reset) # Note: Must be reset with the CPU. self.submodules += mmio_a2w l2fb_a2w = ResetInserter()(axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0)) - self.comb += l2fb_a2w.reset.eq(ResetSignal() | self.reset) + self.comb += l2fb_a2w.reset.eq(ResetSignal() | self.reset) # Note: Must be reset with the CPU. self.submodules += l2fb_a2w - # add verilog sources + # Add Verilog sources. self.add_sources(platform, variant) def set_reset_address(self, reset_address): diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index e49475bb1..4c6c0792a 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -13,9 +13,11 @@ from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = ["standard"] +# SERV --------------------------------------------------------------------------------------------- class SERV(CPU): name = "serv" @@ -26,8 +28,9 @@ class SERV(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV32 linker_output_format = "elf32-littleriscv" nop = "nop" - io_regions = {0x80000000: 0x80000000} # origin, length + io_regions = {0x80000000: 0x80000000} # Origin, Length. + # GCC Flags. @property def gcc_flags(self): flags = "-march=rv32i " @@ -41,26 +44,26 @@ class SERV(CPU): self.reset = Signal() self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() - self.periph_buses = [ibus, dbus] - self.memory_buses = [] + self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # self.cpu_params = dict( - # clock / reset + # Clk / Rst i_clk = ClockSignal(), i_i_rst = ResetSignal() | self.reset, - # timer irq + # Timer IRQ. i_i_timer_irq = 0, - # ibus + # Ibus. o_o_ibus_adr = Cat(Signal(2), ibus.adr), o_o_ibus_cyc = ibus.cyc, i_i_ibus_rdt = ibus.dat_r, i_i_ibus_ack = ibus.ack, - # dbus + # Dbus. o_o_dbus_adr = Cat(Signal(2), dbus.adr), o_o_dbus_dat = dbus.dat_w, o_o_dbus_sel = dbus.sel, @@ -75,7 +78,7 @@ class SERV(CPU): dbus.stb.eq(dbus.cyc), ] - # add verilog sources + # Add Verilog sources self.add_sources(platform) def set_reset_address(self, reset_address): diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index fa6095c45..fd2ad45fa 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -19,6 +19,7 @@ from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = { "minimal": "VexRiscv_Min", @@ -38,6 +39,7 @@ CPU_VARIANTS = { "secure+debug": "VexRiscv_SecureDebug", } +# GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { # /-------- Base ISA @@ -64,6 +66,7 @@ GCC_FLAGS = { "secure+debug": "-march=rv32ima -mabi=ilp32", } +# VexRiscv Timer ----------------------------------------------------------------------------------- class VexRiscvTimer(Module, AutoCSR): def __init__(self): @@ -83,6 +86,7 @@ class VexRiscvTimer(Module, AutoCSR): self.comb += self.interrupt.eq(time >= time_cmp) +# VexRiscv ----------------------------------------------------------------------------------------- class VexRiscv(CPU, AutoCSR): name = "vexriscv" @@ -95,6 +99,7 @@ class VexRiscv(CPU, AutoCSR): nop = "nop" io_regions = {0x80000000: 0x80000000} # origin, length + # Memory Mapping. @property def mem_map(self): return { @@ -105,6 +110,7 @@ class VexRiscv(CPU, AutoCSR): "vexriscv_debug": 0xf00f0000, } + # GCC Flags. @property def gcc_flags(self): flags = GCC_FLAGS[self.variant] @@ -120,43 +126,43 @@ class VexRiscv(CPU, AutoCSR): self.interrupt = Signal(32) self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() - self.periph_buses = [ibus, dbus] - self.memory_buses = [] + self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # self.cpu_params = dict( - i_clk = ClockSignal(), - i_reset = ResetSignal() | self.reset, + i_clk = ClockSignal(), + i_reset = ResetSignal() | self.reset, - i_externalInterruptArray = self.interrupt, - i_timerInterrupt = 0, - i_softwareInterrupt = 0, + i_externalInterruptArray = self.interrupt, + i_timerInterrupt = 0, + i_softwareInterrupt = 0, - o_iBusWishbone_ADR = ibus.adr, - o_iBusWishbone_DAT_MOSI = ibus.dat_w, - o_iBusWishbone_SEL = ibus.sel, - o_iBusWishbone_CYC = ibus.cyc, - o_iBusWishbone_STB = ibus.stb, - o_iBusWishbone_WE = ibus.we, - o_iBusWishbone_CTI = ibus.cti, - o_iBusWishbone_BTE = ibus.bte, - i_iBusWishbone_DAT_MISO = ibus.dat_r, - i_iBusWishbone_ACK = ibus.ack, - i_iBusWishbone_ERR = ibus.err, + o_iBusWishbone_ADR = ibus.adr, + o_iBusWishbone_DAT_MOSI = ibus.dat_w, + o_iBusWishbone_SEL = ibus.sel, + o_iBusWishbone_CYC = ibus.cyc, + o_iBusWishbone_STB = ibus.stb, + o_iBusWishbone_WE = ibus.we, + o_iBusWishbone_CTI = ibus.cti, + o_iBusWishbone_BTE = ibus.bte, + i_iBusWishbone_DAT_MISO = ibus.dat_r, + i_iBusWishbone_ACK = ibus.ack, + i_iBusWishbone_ERR = ibus.err, - o_dBusWishbone_ADR = dbus.adr, - o_dBusWishbone_DAT_MOSI = dbus.dat_w, - o_dBusWishbone_SEL = dbus.sel, - o_dBusWishbone_CYC = dbus.cyc, - o_dBusWishbone_STB = dbus.stb, - o_dBusWishbone_WE = dbus.we, - o_dBusWishbone_CTI = dbus.cti, - o_dBusWishbone_BTE = dbus.bte, - i_dBusWishbone_DAT_MISO = dbus.dat_r, - i_dBusWishbone_ACK = dbus.ack, - i_dBusWishbone_ERR = dbus.err - ) + o_dBusWishbone_ADR = dbus.adr, + o_dBusWishbone_DAT_MOSI = dbus.dat_w, + o_dBusWishbone_SEL = dbus.sel, + o_dBusWishbone_CYC = dbus.cyc, + o_dBusWishbone_STB = dbus.stb, + o_dBusWishbone_WE = dbus.we, + o_dBusWishbone_CTI = dbus.cti, + o_dBusWishbone_BTE = dbus.bte, + i_dBusWishbone_DAT_MISO = dbus.dat_r, + i_dBusWishbone_ACK = dbus.ack, + i_dBusWishbone_ERR = dbus.err + ) if with_timer: self.add_timer() @@ -186,10 +192,8 @@ class VexRiscv(CPU, AutoCSR): self.debug_bus = wishbone.Interface() - self.sync += [ - self.debug_bus.dat_r.eq(self.o_rsp_data), - debug_reset.eq(reset_debug_logic | ResetSignal()), - ] + self.sync += self.debug_bus.dat_r.eq(self.o_rsp_data) + self.sync += debug_reset.eq(reset_debug_logic | ResetSignal()) self.sync += [ # CYC is held high for the duration of the transfer. @@ -237,9 +241,9 @@ class VexRiscv(CPU, AutoCSR): ] self.cpu_params.update( - i_reset=ResetSignal() | self.reset | debug_reset, - i_iBusWishbone_ERR=self.ibus.err | ibus_err, - i_dBusWishbone_ERR=self.dbus.err | dbus_err, + i_reset = ResetSignal() | self.reset | debug_reset, + i_iBusWishbone_ERR = self.ibus.err | ibus_err, + i_dBusWishbone_ERR = self.dbus.err | dbus_err, i_debugReset = ResetSignal(), i_debug_bus_cmd_valid = self.i_cmd_valid, i_debug_bus_cmd_payload_wr = self.i_cmd_payload_wr, @@ -267,8 +271,8 @@ class VexRiscv(CPU, AutoCSR): def add_soc_components(self, soc, soc_region_cls): if "debug" in self.variant: - soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False)) - + soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls( + origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False)) def use_external_variant(self, variant_filename): self.external_variant = True diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 16be85b53..3b95b73aa 100644 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -18,13 +18,16 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 import os +class Open(Signal): pass + +# Variants ----------------------------------------------------------------------------------------- CPU_VARIANTS = { "standard": "VexRiscv", "linux": "VexRiscv", # Similar to standard. } -class Open(Signal): pass +# VexRiscv SMP ------------------------------------------------------------------------------------- class VexRiscvSMP(CPU): name = "vexriscv" @@ -35,8 +38,9 @@ class VexRiscvSMP(CPU): gcc_triple = CPU_GCC_TRIPLE_RISCV32 linker_output_format = "elf32-littleriscv" nop = "nop" - io_regions = {0x80000000: 0x80000000} # origin, length + io_regions = {0x80000000: 0x80000000} # Origin, Length. + # Default parameters. cpu_count = 1 dcache_size = 4096 icache_size = 4096 @@ -53,6 +57,7 @@ class VexRiscvSMP(CPU): cpu_per_fpu = 4 with_rvc = False + # Command line configuration arguments. @staticmethod def args_fill(parser): parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int) @@ -102,7 +107,7 @@ class VexRiscvSMP(CPU): if(args.with_rvc): VexRiscvSMP.with_rvc = True - + # ABI. @staticmethod def get_abi(): abi = "ilp32" @@ -110,6 +115,7 @@ class VexRiscvSMP(CPU): abi +="d" return abi + # Arch. @staticmethod def get_arch(): arch = "rv32ima" @@ -119,6 +125,7 @@ class VexRiscvSMP(CPU): arch += "c" return arch + # Memory Mapping. @property def mem_map(self): return { @@ -130,6 +137,7 @@ class VexRiscvSMP(CPU): "plic": 0xf0c00000, } + # GCC Flags. @property def gcc_flags(self): flags = f" -march={VexRiscvSMP.get_arch()} -mabi={VexRiscvSMP.get_abi()}" @@ -137,6 +145,7 @@ class VexRiscvSMP(CPU): flags += f" -DUART_POLLING" return flags + # Cluster Name Generation. @staticmethod def generate_cluster_name(): ldw = f"Ldw{VexRiscvSMP.litedram_width}" @@ -158,9 +167,10 @@ class VexRiscvSMP(CPU): f"{'_Fpu' + str(VexRiscvSMP.cpu_per_fpu) if VexRiscvSMP.with_fpu else ''}" \ f"{'_Rvc' if VexRiscvSMP.with_rvc else ''}" + # Default Configs Generation. @staticmethod def generate_default_configs(): - # Single cores + # Single cores. for data_width in [16, 32, 64, 128]: VexRiscvSMP.litedram_width = data_width VexRiscvSMP.icache_width = 32 @@ -168,23 +178,23 @@ class VexRiscvSMP(CPU): VexRiscvSMP.coherent_dma = False VexRiscvSMP.cpu_count = 1 - # Low cache amount + # Low cache amount. VexRiscvSMP.dcache_size = 4096 VexRiscvSMP.icache_size = 4096 VexRiscvSMP.dcache_ways = 1 VexRiscvSMP.icache_ways = 1 - # Without DMA + # Without DMA. VexRiscvSMP.coherent_dma = False VexRiscvSMP.generate_cluster_name() VexRiscvSMP.generate_netlist() - # With DMA + # With DMA. VexRiscvSMP.coherent_dma = True VexRiscvSMP.generate_cluster_name() VexRiscvSMP.generate_netlist() - # High cache amount + # High cache amount. VexRiscvSMP.dcache_size = 8192 VexRiscvSMP.icache_size = 8192 VexRiscvSMP.dcache_ways = 2 @@ -192,17 +202,17 @@ class VexRiscvSMP(CPU): VexRiscvSMP.icache_width = 32 if data_width < 64 else 64 VexRiscvSMP.dcache_width = 32 if data_width < 64 else 64 - # Without DMA + # Without DMA. VexRiscvSMP.coherent_dma = False VexRiscvSMP.generate_cluster_name() VexRiscvSMP.generate_netlist() - # With DMA + # With DMA. VexRiscvSMP.coherent_dma = True VexRiscvSMP.generate_cluster_name() VexRiscvSMP.generate_netlist() - # Multi cores + # Multi cores. for core_count in [2,4]: VexRiscvSMP.litedram_width = 128 VexRiscvSMP.icache_width = 64 @@ -216,6 +226,7 @@ class VexRiscvSMP(CPU): VexRiscvSMP.generate_cluster_name() VexRiscvSMP.generate_netlist() + # Netlist Generation. @staticmethod def generate_netlist(): print(f"Generating cluster netlist") @@ -260,40 +271,40 @@ class VexRiscvSMP(CPU): self.interrupt = Signal(32) self.pbus = pbus = wishbone.Interface() - self.periph_buses = [pbus] - self.memory_buses = [] # Added dynamically + self.periph_buses = [pbus] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # self.cpu_params = dict( - # Clk / Rst + # Clk / Rst. i_debugCd_external_clk = ClockSignal(), i_debugCd_external_reset = ResetSignal() | self.reset, - # Interrupts - i_interrupts = self.interrupt, + # Interrupts. + i_interrupts = self.interrupt, - # JTAG - i_jtag_clk = self.jtag_clk, - i_debugPort_enable = self.jtag_enable, - i_debugPort_capture = self.jtag_capture, - i_debugPort_shift = self.jtag_shift, - i_debugPort_update = self.jtag_update, - i_debugPort_reset = self.jtag_reset, - i_debugPort_tdi = self.jtag_tdi, - o_debugPort_tdo = self.jtag_tdo, + # JTAG. + i_jtag_clk = self.jtag_clk, + i_debugPort_enable = self.jtag_enable, + i_debugPort_capture = self.jtag_capture, + i_debugPort_shift = self.jtag_shift, + i_debugPort_update = self.jtag_update, + i_debugPort_reset = self.jtag_reset, + i_debugPort_tdi = self.jtag_tdi, + o_debugPort_tdo = self.jtag_tdo, - # Peripheral Bus (Master) - o_peripheral_CYC = pbus.cyc, - o_peripheral_STB = pbus.stb, - i_peripheral_ACK = pbus.ack, - o_peripheral_WE = pbus.we, - o_peripheral_ADR = pbus.adr, - i_peripheral_DAT_MISO = pbus.dat_r, - o_peripheral_DAT_MOSI = pbus.dat_w, - o_peripheral_SEL = pbus.sel, - i_peripheral_ERR = pbus.err, - o_peripheral_CTI = pbus.cti, - o_peripheral_BTE = pbus.bte + # Peripheral Bus (Master). + o_peripheral_CYC = pbus.cyc, + o_peripheral_STB = pbus.stb, + i_peripheral_ACK = pbus.ack, + o_peripheral_WE = pbus.we, + o_peripheral_ADR = pbus.adr, + i_peripheral_DAT_MISO = pbus.dat_r, + o_peripheral_DAT_MOSI = pbus.dat_w, + o_peripheral_SEL = pbus.sel, + i_peripheral_ERR = pbus.err, + o_peripheral_CTI = pbus.cti, + o_peripheral_BTE = pbus.bte ) if VexRiscvSMP.coherent_dma: @@ -301,6 +312,7 @@ class VexRiscvSMP(CPU): dma_bus_stall = Signal() dma_bus_inhibit = Signal() self.cpu_params.update( + # DMA Bus (Slave). i_dma_wishbone_CYC = dma_bus.cyc, i_dma_wishbone_STB = dma_bus.stb & ~dma_bus_inhibit, o_dma_wishbone_ACK = dma_bus.ack, @@ -388,7 +400,7 @@ class VexRiscvSMP(CPU): self.memory_buses.append(ibus) self.memory_buses.append(dbus) self.cpu_params.update( - # Instruction Memory Bus (Master) + # Instruction Memory Bus (Master). o_iBridge_dram_cmd_valid = ibus.cmd.valid, i_iBridge_dram_cmd_ready = ibus.cmd.ready, o_iBridge_dram_cmd_payload_we = ibus.cmd.we, @@ -401,7 +413,7 @@ class VexRiscvSMP(CPU): o_iBridge_dram_rdata_ready = ibus.rdata.ready, i_iBridge_dram_rdata_payload_data = ibus.rdata.data, - # Data Memory Bus (Master) + # Data Memory Bus (Master). o_dBridge_dram_cmd_valid = dbus.cmd.valid, i_dBridge_dram_cmd_ready = dbus.cmd.ready, o_dBridge_dram_cmd_payload_we = dbus.cmd.we, @@ -419,6 +431,6 @@ class VexRiscvSMP(CPU): assert hasattr(self, "reset_address") self.specials += Instance(self.cluster_name, **self.cpu_params) - # Add verilog sources + # Add Verilog sources self.add_sources(self.platform) diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py index e92868a45..ef4239d59 100644 --- a/litex/soc/cores/cpu/zynq7000/core.py +++ b/litex/soc/cores/cpu/zynq7000/core.py @@ -15,6 +15,7 @@ from litex.soc.interconnect import axi from litex.soc.cores.cpu import CPU +# Zynq 7000 ---------------------------------------------------------------------------------------- class Zynq7000(CPU): variants = ["standard"] @@ -26,8 +27,9 @@ class Zynq7000(CPU): gcc_triple = "arm-xilinx-eabi" linker_output_format = "elf32-littlearm" nop = "nop" - io_regions = {0x00000000: 0x100000000} # origin, length + io_regions = {0x00000000: 0x100000000} # Origin, Length. + # Memory Mapping. @property def mem_map(self): return {"csr": 0x00000000} @@ -35,15 +37,16 @@ class Zynq7000(CPU): def __init__(self, platform, variant): self.platform = platform self.reset = Signal() - self.periph_buses = [] - self.memory_buses = [] + self.periph_buses = [] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). - self.axi_gp_masters = [] - self.axi_gp_slaves = [] - self.axi_hp_slaves = [] + self.axi_gp_masters = [] # General Purpose AXI Masters. + self.axi_gp_slaves = [] # General Purpose AXI Slaves. + self.axi_hp_slaves = [] # High Performance AXI Slaves. # # # + # PS7 Clocking. self.clock_domains.cd_ps7 = ClockDomain() # PS7 (Minimal) ---------------------------------------------------------------------------- @@ -52,39 +55,39 @@ class Zynq7000(CPU): ps7_rst_n = Signal() ps7_ddram_pads = platform.request("ps7_ddram") self.cpu_params = dict( - # Clk/Rst - io_PS_CLK = platform.request("ps7_clk"), - io_PS_PORB = platform.request("ps7_porb"), - io_PS_SRSTB = platform.request("ps7_srstb"), + # Clk / Rst. + io_PS_CLK = platform.request("ps7_clk"), + io_PS_PORB = platform.request("ps7_porb"), + io_PS_SRSTB = platform.request("ps7_srstb"), - # MIO - io_MIO = platform.request("ps7_mio"), + # MIO. + io_MIO = platform.request("ps7_mio"), - # DDRAM - io_DDR_Addr = ps7_ddram_pads.addr, - io_DDR_BankAddr = ps7_ddram_pads.ba, - io_DDR_CAS_n = ps7_ddram_pads.cas_n, - io_DDR_Clk_n = ps7_ddram_pads.ck_n, - io_DDR_Clk = ps7_ddram_pads.ck_p, - io_DDR_CKE = ps7_ddram_pads.cke, - io_DDR_CS_n = ps7_ddram_pads.cs_n, - io_DDR_DM = ps7_ddram_pads.dm, - io_DDR_DQ = ps7_ddram_pads.dq, - io_DDR_DQS_n = ps7_ddram_pads.dqs_n, - io_DDR_DQS = ps7_ddram_pads.dqs_p, - io_DDR_ODT = ps7_ddram_pads.odt, - io_DDR_RAS_n = ps7_ddram_pads.ras_n, - io_DDR_DRSTB = ps7_ddram_pads.reset_n, - io_DDR_WEB = ps7_ddram_pads.we_n, - io_DDR_VRN = ps7_ddram_pads.vrn, - io_DDR_VRP = ps7_ddram_pads.vrp, + # DDRAM. + io_DDR_Addr = ps7_ddram_pads.addr, + io_DDR_BankAddr = ps7_ddram_pads.ba, + io_DDR_CAS_n = ps7_ddram_pads.cas_n, + io_DDR_Clk_n = ps7_ddram_pads.ck_n, + io_DDR_Clk = ps7_ddram_pads.ck_p, + io_DDR_CKE = ps7_ddram_pads.cke, + io_DDR_CS_n = ps7_ddram_pads.cs_n, + io_DDR_DM = ps7_ddram_pads.dm, + io_DDR_DQ = ps7_ddram_pads.dq, + io_DDR_DQS_n = ps7_ddram_pads.dqs_n, + io_DDR_DQS = ps7_ddram_pads.dqs_p, + io_DDR_ODT = ps7_ddram_pads.odt, + io_DDR_RAS_n = ps7_ddram_pads.ras_n, + io_DDR_DRSTB = ps7_ddram_pads.reset_n, + io_DDR_WEB = ps7_ddram_pads.we_n, + io_DDR_VRN = ps7_ddram_pads.vrn, + io_DDR_VRP = ps7_ddram_pads.vrp, - # USB0 + # USB0. i_USB0_VBUS_PWRFAULT = 0, - # Fabric Clk/Rst - o_FCLK_CLK0 = ClockSignal("ps7"), - o_FCLK_RESET0_N = ps7_rst_n + # Fabric Clk / Rst. + o_FCLK_CLK0 = ClockSignal("ps7"), + o_FCLK_RESET0_N = ps7_rst_n ) self.specials += AsyncResetSynchronizer(self.cd_ps7, ~ps7_rst_n) @@ -182,7 +185,7 @@ class Zynq7000(CPU): if config is not None: self.add_ps7_config(config) - # AXI GP Master -------------------------------------------------------------------------------- + # AXI General Purpose Master ------------------------------------------------------------------- def add_axi_gp_master(self): assert len(self.axi_gp_masters) < 2 @@ -190,10 +193,10 @@ class Zynq7000(CPU): axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12) self.axi_gp_masters.append(axi_gpn) self.cpu_params.update({ - # AXI GP clk + # AXI GP clk. f"i_M_AXI_GP{n}_ACLK" : ClockSignal("ps7"), - # AXI GP aw + # AXI GP aw. f"o_M_AXI_GP{n}_AWVALID" : axi_gpn.aw.valid, f"i_M_AXI_GP{n}_AWREADY" : axi_gpn.aw.ready, f"o_M_AXI_GP{n}_AWADDR" : axi_gpn.aw.addr, @@ -206,7 +209,7 @@ class Zynq7000(CPU): f"o_M_AXI_GP{n}_AWCACHE" : axi_gpn.aw.cache, f"o_M_AXI_GP{n}_AWQOS" : axi_gpn.aw.qos, - # AXI GP w + # AXI GP w. f"o_M_AXI_GP{n}_WVALID" : axi_gpn.w.valid, f"o_M_AXI_GP{n}_WLAST" : axi_gpn.w.last, f"i_M_AXI_GP{n}_WREADY" : axi_gpn.w.ready, @@ -214,13 +217,13 @@ class Zynq7000(CPU): f"o_M_AXI_GP{n}_WDATA" : axi_gpn.w.data, f"o_M_AXI_GP{n}_WSTRB" : axi_gpn.w.strb, - # AXI GP b + # AXI GP b. f"i_M_AXI_GP{n}_BVALID" : axi_gpn.b.valid, f"o_M_AXI_GP{n}_BREADY" : axi_gpn.b.ready, f"i_M_AXI_GP{n}_BID" : axi_gpn.b.id, f"i_M_AXI_GP{n}_BRESP" : axi_gpn.b.resp, - # AXI GP ar + # AXI GP ar. f"o_M_AXI_GP{n}_ARVALID" : axi_gpn.ar.valid, f"i_M_AXI_GP{n}_ARREADY" : axi_gpn.ar.ready, f"o_M_AXI_GP{n}_ARADDR" : axi_gpn.ar.addr, @@ -233,7 +236,7 @@ class Zynq7000(CPU): f"o_M_AXI_GP{n}_ARCACHE" : axi_gpn.ar.cache, f"o_M_AXI_GP{n}_ARQOS" : axi_gpn.ar.qos, - # AXI GP r + # AXI GP r. f"i_M_AXI_GP{n}_RVALID" : axi_gpn.r.valid, f"o_M_AXI_GP{n}_RREADY" : axi_gpn.r.ready, f"i_M_AXI_GP{n}_RLAST" : axi_gpn.r.last, @@ -243,12 +246,12 @@ class Zynq7000(CPU): }) return axi_gpn - # AXI GP Slave --------------------------------------------------------------------------------- + # AXI General Purpose Slave -------------------------------------------------------------------- def add_axi_gp_slave(self): raise NotImplementedError - # AXI HP Slave --------------------------------------------------------------------------------- + # AXI High Performance Slave ------------------------------------------------------------------- def add_axi_hp_slave(self): assert len(self.axi_hp_slaves) < 4 @@ -256,10 +259,10 @@ class Zynq7000(CPU): axi_hpn = axi.AXIInterface(data_width=64, address_width=32, id_width=6) self.axi_hp_slaves.append(axi_hpn) self.cpu_params.update({ - # AXI HP0 clk + # AXI HP0 clk. f"i_S_AXI_HP{n}_ACLK" : ClockSignal("ps7"), - # AXI HP0 aw + # AXI HP0 aw. f"i_S_AXI_HP{n}_AWVALID" : axi_hpn.aw.valid, f"o_S_AXI_HP{n}_AWREADY" : axi_hpn.aw.ready, f"i_S_AXI_HP{n}_AWADDR" : axi_hpn.aw.addr, @@ -272,7 +275,7 @@ class Zynq7000(CPU): f"i_S_AXI_HP{n}_AWCACHE" : axi_hpn.aw.cache, f"i_S_AXI_HP{n}_AWQOS" : axi_hpn.aw.qos, - # AXI HP0 w + # AXI HP0 w. f"i_S_AXI_HP{n}_WVALID" : axi_hpn.w.valid, f"i_S_AXI_HP{n}_WLAST" : axi_hpn.w.last, f"o_S_AXI_HP{n}_WREADY" : axi_hpn.w.ready, @@ -280,13 +283,13 @@ class Zynq7000(CPU): f"i_S_AXI_HP{n}_WDATA" : axi_hpn.w.data, f"i_S_AXI_HP{n}_WSTRB" : axi_hpn.w.strb, - # AXI HP0 b + # AXI HP0 b. f"o_S_AXI_HP{n}_BVALID" : axi_hpn.b.valid, f"i_S_AXI_HP{n}_BREADY" : axi_hpn.b.ready, f"o_S_AXI_HP{n}_BID" : axi_hpn.b.id, f"o_S_AXI_HP{n}_BRESP" : axi_hpn.b.resp, - # AXI HP0 ar + # AXI HP0 ar. f"i_S_AXI_HP{n}_ARVALID" : axi_hpn.ar.valid, f"o_S_AXI_HP{n}_ARREADY" : axi_hpn.ar.ready, f"i_S_AXI_HP{n}_ARADDR" : axi_hpn.ar.addr, @@ -299,7 +302,7 @@ class Zynq7000(CPU): f"i_S_AXI_HP{n}_ARCACHE" : axi_hpn.ar.cache, f"i_S_AXI_HP{n}_ARQOS" : axi_hpn.ar.qos, - # AXI HP0 r + # AXI HP0 r. f"o_S_AXI_HP{n}_RVALID" : axi_hpn.r.valid, f"i_S_AXI_HP{n}_RREADY" : axi_hpn.r.ready, f"o_S_AXI_HP{n}_RLAST" : axi_hpn.r.last,