diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 00277735d..c75a0d956 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -270,7 +270,7 @@ def soc_core_args(parser):
     parser.add_argument("--no-ctrl", action="store_true", help="Disable Controller (default=False).")
 
     # ROM parameters
-    parser.add_argument("--integrated-rom-size", default=0x10000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (default=64KB, automatically resized to BIOS size when smaller).")
+    parser.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (default=128KB, automatically resized to BIOS size when smaller).")
     parser.add_argument("--integrated-rom-file", default=None,    type=str,      help="Integrated (BIOS) ROM binary file.")
 
     # SRAM parameters