diff --git a/migen/actorlib/fifo.py b/migen/actorlib/fifo.py
index 3d6f036da..817941c77 100644
--- a/migen/actorlib/fifo.py
+++ b/migen/actorlib/fifo.py
@@ -2,40 +2,31 @@ from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.genlib import fifo
 
-def FIFOWrapper(sink, source, fifo):
-	return [
-			sink.ack.eq(fifo.writable),
-			fifo.we.eq(sink.stb & sink.ack),
-			fifo.din.eq(sink.payload),
+class _FIFOActor(Module):
+	def __init__(self, fifo_class, layout, depth):
+		self.sink = Sink(layout)
+		self.source = Source(layout)
+		self.busy = Signal()
 
-			source.stb.eq(fifo.readable),
-			source.payload.eq(fifo.dout),
-			fifo.re.eq(source.ack)
-	]
+		###
 
-class SyncFIFO(Module):
+		self.submodules.fifo = fifo_class(layout, depth)
+
+		self.comb += [
+			self.sink.ack.eq(self.fifo.writable),
+			self.fifo.we.eq(self.sink.stb & self.sink.ack),
+			self.fifo.din.eq(self.sink.payload),
+
+			self.source.stb.eq(self.fifo.readable),
+			self.source.payload.eq(self.fifo.dout),
+			self.fifo.re.eq(self.source.ack)
+		]
+
+
+class SyncFIFO(_FIFOActor):
 	def __init__(self, layout, depth):
+		_FIFOActor.__init__(self, fifo.SyncFIFO, layout, depth)
 
-		self.sink = Sink(layout)
-		self.source = Source(layout)
-		self.busy = Signal()
-
-		_fifo = fifo.SyncFIFO(layout, depth)		
-
-		self.submodules += _fifo
-
-		self.comb += FIFOWrapper(self.sink, self.source, _fifo)
-
-class AsyncFIFO(Module):
-	def __init__(self, layout, depth, cd_write="write", cd_read="read"):
-
-		self.sink = Sink(layout)
-		self.source = Source(layout)
-		self.busy = Signal()
-
-		_fifo = RenameClockDomains(fifo.AsyncFIFO(layout, depth),
-			{"write": cd_write, "read": cd_read})
-		self.submodules += _fifo
-
-		self.comb += FIFOWrapper(self.sink, self.source, _fifo)
-		
\ No newline at end of file
+class AsyncFIFO(_FIFOActor):
+	def __init__(self, layout, depth):
+		_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)