From 121eaba722e0b0b732003473630362dba4d48182 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 1 May 2018 00:46:26 +0200 Subject: [PATCH] soc/intergration/soc_core: don't delete uart/timer0 interrupts --- litex/soc/integration/soc_core.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 5ef85397e..c439f55d1 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -146,8 +146,8 @@ class SoCCore(Module): else: self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = uart.UART(self.uart_phy) - else: - del self.soc_interrupt_map["uart"] + #else: + # del self.soc_interrupt_map["uart"] if ident: if ident_version: @@ -158,8 +158,8 @@ class SoCCore(Module): if with_timer: self.submodules.timer0 = timer.Timer() - else: - del self.soc_interrupt_map["timer0"] + #else: + # del self.soc_interrupt_map["timer0"] # Invert the interrupt map. interrupt_rmap = {}