From 122e060a5ec46716d1052447ca5f3c7da916287d Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 16 May 2024 19:30:15 +0200 Subject: [PATCH] update vexii --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 359eb4dad..83743b914 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -130,7 +130,7 @@ class VexiiRiscv(CPU): print(args) if args.update_repo != "no": - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "c330b794" if args.update_repo=="recommended" else None) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "139a1bd6" if args.update_repo=="recommended" else None)