diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index b9750bba5..81af2b0c1 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -197,23 +197,23 @@ class XilinxVivadoToolchain:
         # The asynchronous input to a MultiReg is a false path
         platform.add_platform_command(
             "set_false_path -quiet "
-            "-to [get_nets -filter {{mr_ff == TRUE}}]"
+            "-to [get_nets -quiet -filter {{mr_ff == TRUE}}]"
         )
         # The asychronous reset input to the AsyncResetSynchronizer is a false
         # path
         platform.add_platform_command(
             "set_false_path -quiet "
-            "-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
-                "-of [get_cells -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
+            "-to [get_pins -quiet -filter {{REF_PIN_NAME == PRE}} "
+                "-of [get_cells -quiet -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
         )
         # clock_period-2ns to resolve metastability on the wire between the
         # AsyncResetSynchronizer FFs
         platform.add_platform_command(
             "set_max_delay 2 -quiet "
-            "-from [get_pins -filter {{REF_PIN_NAME == Q}} "
-                "-of [get_cells -filter {{ars_ff1 == TRUE}}]] "
-            "-to [get_pins -filter {{REF_PIN_NAME == D}} "
-                "-of [get_cells -filter {{ars_ff2 == TRUE}}]]"
+            "-from [get_pins -quiet -filter {{REF_PIN_NAME == Q}} "
+                "-of [get_cells -quiet -filter {{ars_ff1 == TRUE}}]] "
+            "-to [get_pins -quiet -filter {{REF_PIN_NAME == D}} "
+                "-of [get_cells -quiet -filter {{ars_ff2 == TRUE}}]]"
         )
 
     def build(self, platform, fragment, build_dir="build", build_name="top",