diff --git a/test/test_wishbone.py b/test/test_wishbone.py index c18107f5f..eb895612c 100644 --- a/test/test_wishbone.py +++ b/test/test_wishbone.py @@ -164,41 +164,46 @@ class TestWishbone(unittest.TestCase): dut = DUT() run_simulation(dut, [generator(dut), checker(dut)]) - def test_origin_remap_word(self): + + def origin_remap_test(self, addressing="byte"): + adr_div = { + "byte": 1, + "word": 4, + }[addressing] def generator(dut): - yield from dut.master.write(0x0000_0000//4, 0) - yield from dut.master.write(0x0000_0004//4, 0) - yield from dut.master.write(0x0000_0008//4, 0) - yield from dut.master.write(0x0000_000c//4, 0) - yield from dut.master.write(0x1000_0000//4, 0) - yield from dut.master.write(0x1000_0004//4, 0) - yield from dut.master.write(0x1000_0008//4, 0) - yield from dut.master.write(0x1000_000c//4, 0) + yield from dut.master.write(0x0000_0000//adr_div, 0) + yield from dut.master.write(0x0000_0004//adr_div, 0) + yield from dut.master.write(0x0000_0008//adr_div, 0) + yield from dut.master.write(0x0000_000c//adr_div, 0) + yield from dut.master.write(0x1000_0000//adr_div, 0) + yield from dut.master.write(0x1000_0004//adr_div, 0) + yield from dut.master.write(0x1000_0008//adr_div, 0) + yield from dut.master.write(0x1000_000c//adr_div, 0) def checker(dut): yield dut.slave.ack.eq(1) while (yield dut.slave.stb) == 0: yield - self.assertEqual((yield dut.slave.adr), 0x0001_0000//4) + self.assertEqual((yield dut.slave.adr), 0x0001_0000//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_0004//4) + self.assertEqual((yield dut.slave.adr), 0x0001_0004//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_0008//4) + self.assertEqual((yield dut.slave.adr), 0x0001_0008//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_000c//4) + self.assertEqual((yield dut.slave.adr), 0x0001_000c//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_0000//4) + self.assertEqual((yield dut.slave.adr), 0x0001_0000//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_0004//4) + self.assertEqual((yield dut.slave.adr), 0x0001_0004//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_0008//4) + self.assertEqual((yield dut.slave.adr), 0x0001_0008//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x0001_000c//4) + self.assertEqual((yield dut.slave.adr), 0x0001_000c//adr_div) class DUT(LiteXModule): def __init__(self): - self.master = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.master = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) + self.slave = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) self.remapper = wishbone.Remapper(self.master, self.slave, origin = 0x0001_0000, size = 0x1000_0000, @@ -206,30 +211,40 @@ class TestWishbone(unittest.TestCase): dut = DUT() run_simulation(dut, [generator(dut), checker(dut)]) - def test_region_remap_byte(self): + def test_origin_remap_byte(self): + self.origin_remap_test(addressing="byte") + + def test_origin_remap_word(self): + self.origin_remap_test(addressing="word") + + def region_remap_test(self, addressing="byte"): + adr_div = { + "byte": 1, + "word": 4, + }[addressing] def generator(dut): - yield from dut.master.write(0x0000_0000, 0) - yield from dut.master.write(0x0001_0004, 0) - yield from dut.master.write(0x0002_0008, 0) - yield from dut.master.write(0x0003_000c, 0) + yield from dut.master.write(0x0000_0000//adr_div, 0) + yield from dut.master.write(0x0001_0004//adr_div, 0) + yield from dut.master.write(0x0002_0008//adr_div, 0) + yield from dut.master.write(0x0003_000c//adr_div, 0) def checker(dut): yield dut.slave.ack.eq(1) while (yield dut.slave.stb) == 0: yield - self.assertEqual((yield dut.slave.adr), 0x0000_0000) + self.assertEqual((yield dut.slave.adr), 0x0000_0000//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x1000_0004) + self.assertEqual((yield dut.slave.adr), 0x1000_0004//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x2000_0008) + self.assertEqual((yield dut.slave.adr), 0x2000_0008//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x3000_000c) + self.assertEqual((yield dut.slave.adr), 0x3000_000c//adr_div) yield class DUT(LiteXModule): def __init__(self): - self.master = wishbone.Interface(data_width=32, address_width=32, addressing="byte") - self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.master = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) + self.slave = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) self.remapper = wishbone.Remapper(self.master, self.slave, src_regions = [ SoCRegion(origin=0x0000_0000, size=0x1000), @@ -247,67 +262,36 @@ class TestWishbone(unittest.TestCase): dut = DUT() run_simulation(dut, [generator(dut), checker(dut)]) + def test_region_remap_byte(self): + self.region_remap_test(addressing="byte") + def test_region_remap_word(self): + self.region_remap_test(addressing="word") + + def origin_region_remap_test(self, addressing="byte"): + adr_div = { + "byte": 1, + "word": 4, + }[addressing] def generator(dut): - yield from dut.master.write(0x0000_0000//4, 0) - yield from dut.master.write(0x0001_0004//4, 0) - yield from dut.master.write(0x0002_0008//4, 0) - yield from dut.master.write(0x0003_000c//4, 0) + yield from dut.master.write(0x0000_0000//adr_div, 0) + yield from dut.master.write(0x0002_0000//adr_div, 0) def checker(dut): yield dut.slave.ack.eq(1) while (yield dut.slave.stb) == 0: yield - self.assertEqual((yield dut.slave.adr), 0x0000_0000//4) + self.assertEqual((yield dut.slave.adr), 0x1000_0000//adr_div) yield - self.assertEqual((yield dut.slave.adr), 0x1000_0004//4) - yield - self.assertEqual((yield dut.slave.adr), 0x2000_0008//4) - yield - self.assertEqual((yield dut.slave.adr), 0x3000_000c//4) - yield - - class DUT(LiteXModule): - def __init__(self): - self.master = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.remapper = wishbone.Remapper(self.master, self.slave, - src_regions = [ - SoCRegion(origin=0x0000_0000, size=0x1000), - SoCRegion(origin=0x0001_0000, size=0x1000), - SoCRegion(origin=0x0002_0000, size=0x1000), - SoCRegion(origin=0x0003_0000, size=0x1000), - ], - dst_regions = [ - SoCRegion(origin=0x0000_0000, size=0x1000), - SoCRegion(origin=0x1000_0000, size=0x1000), - SoCRegion(origin=0x2000_0000, size=0x1000), - SoCRegion(origin=0x3000_0000, size=0x1000), - ] - ) - dut = DUT() - run_simulation(dut, [generator(dut), checker(dut)]) - - def test_origin_region_remap_byte(self): - def generator(dut): - yield from dut.master.write(0x0000_0000, 0) - yield from dut.master.write(0x0002_0000, 0) - - def checker(dut): - yield dut.slave.ack.eq(1) - while (yield dut.slave.stb) == 0: - yield - self.assertEqual((yield dut.slave.adr), 0x1000_0000) - yield - self.assertEqual((yield dut.slave.adr), 0x0003_0000) + self.assertEqual((yield dut.slave.adr), 0x0003_0000//adr_div) yield for i in range(128): yield class DUT(LiteXModule): def __init__(self): - self.master = wishbone.Interface(data_width=32, address_width=32, addressing="byte") - self.slave = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.master = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) + self.slave = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) self.remapper = wishbone.Remapper(self.master, self.slave, origin = 0x1_0000, size = 0x8_0000, @@ -320,3 +304,9 @@ class TestWishbone(unittest.TestCase): ) dut = DUT() run_simulation(dut, [generator(dut), checker(dut)]) + + def test_origin_region_remap_byte(self): + self.origin_region_remap_test(addressing="byte") + + def test_origin_region_remap_word(self): + self.origin_region_remap_test(addressing="word")