From 1335d3cebc32d508fdf98d5770a08c77b3475be3 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 17 Jun 2024 16:35:26 +0200 Subject: [PATCH] soc/cores/cpu/zynq7000/core.py: enable F2P interrupts --- litex/soc/cores/cpu/zynq7000/core.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py index 5b25a1429..eeab07a28 100644 --- a/litex/soc/cores/cpu/zynq7000/core.py +++ b/litex/soc/cores/cpu/zynq7000/core.py @@ -54,6 +54,10 @@ class Zynq7000(CPU): self.axi_gp_slaves = [] # General Purpose AXI Slaves. self.axi_hp_slaves = [] # High Performance AXI Slaves. + # [ 7: 0]: SPI Numbers [68:61] + # [15: 8]: SPI Numbers [91:84] + self.interrupt = Signal(16) + # # # # PS7 Clocking. @@ -62,7 +66,12 @@ class Zynq7000(CPU): # PS7 (Minimal) ---------------------------------------------------------------------------- self.ps7_name = None self.ps7_tcl = [] - self.config = {} + self.config = { + # Enable interrupts by default + "PCW_USE_FABRIC_INTERRUPT" : 1, + "PCW_IRQ_F2P_INTR" : 1, + "PCW_NUM_F2P_INTR_INPUTS" : 16, + } ps7_rst_n = Signal() ps7_ddram_pads = platform.request("ps7_ddram") self.cpu_params = dict( @@ -96,6 +105,9 @@ class Zynq7000(CPU): # USB0. i_USB0_VBUS_PWRFAULT = 0, + # Interrupts PL -> PS. + i_IRQ_F2P = self.interrupt, + # Fabric Clk / Rst. o_FCLK_CLK0 = ClockSignal("ps7"), o_FCLK_RESET0_N = ps7_rst_n